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Tests: Fix --verbose broken display
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@ -31,7 +31,7 @@ module t(/*AUTOARG*/
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// Test loop
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// Test loop
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always @ (posedge clk) begin
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always @ (posedge clk) begin
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`ifdef TEST_VERBOSE
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`ifdef TEST_VERBOSE
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$write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc);
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$write("[%0t] cyc==%0d crc=%x\n", $time, cyc, crc);
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`endif
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`endif
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cyc <= cyc + 1;
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cyc <= cyc + 1;
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crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
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crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
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