mirror of
https://github.com/verilator/verilator.git
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Fix protect-lib without sequential logic (#2492)
* add a test for protect-lib without sequential logic that cause the follwoing error.
%Error: obj_vlt/t_prot_lib_comb/secret/secret.sv:78:14: syntax error, unexpected ')'
78 | always @() begin
| ^
* protect-lib wrapper must contain sequential signal related statements
only if the protected design is a sequential logic.
Diff looks big, but actually just add "if (m_hasClk)" condition.
Signed-off-by: Yutetsu TAKATSUKASA <y.takatsukasa@gmail.com>
This commit is contained in:
Yutetsu TAKATSUKASA
GitHub
parent
1280070abb
commit
c85589371a
@ -60,6 +60,7 @@ private:
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string m_libName;
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string m_topName;
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bool m_foundTop; // Have seen the top module
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bool m_hasClk; // True if the top module has sequential logic
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// VISITORS
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virtual void visit(AstNetlist* nodep) VL_OVERRIDE {
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@ -79,6 +80,8 @@ private:
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UASSERT_OBJ(!m_foundTop, nodep, "Multiple root modules");
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}
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FileLine* fl = nodep->fileline();
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// Need to know the existence of clk before createSvFile()
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m_hasClk = checkIfClockExists(nodep);
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createSvFile(fl);
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createCppFile(fl);
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@ -162,14 +165,16 @@ private:
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txtp->addNodep(m_comboPortsp);
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txtp->addText(fl, ");\n\n");
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seqComment(txtp, fl);
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m_seqPortsp = new AstTextBlock(fl,
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"import \"DPI-C\" function longint " + m_libName
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+ "_protectlib_seq_update"
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"(\n",
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false, true);
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m_seqPortsp->addText(fl, "chandle handle__V\n");
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txtp->addNodep(m_seqPortsp);
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txtp->addText(fl, ");\n\n");
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if (m_hasClk) {
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m_seqPortsp = new AstTextBlock(fl,
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"import \"DPI-C\" function longint " + m_libName
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+ "_protectlib_seq_update"
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"(\n",
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false, true);
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m_seqPortsp->addText(fl, "chandle handle__V\n");
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txtp->addNodep(m_seqPortsp);
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txtp->addText(fl, ");\n\n");
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}
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comboIgnoreComment(txtp, fl);
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m_comboIgnorePortsp = new AstTextBlock(fl,
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"import \"DPI-C\" function void " + m_libName
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@ -192,7 +197,7 @@ private:
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m_tmpDeclsp = new AstTextBlock(fl);
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txtp->addNodep(m_tmpDeclsp);
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txtp->addText(fl, "\ntime last_combo_seqnum__V;\n");
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txtp->addText(fl, "time last_seq_seqnum__V;\n\n");
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if (m_hasClk) { txtp->addText(fl, "time last_seq_seqnum__V;\n\n"); }
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// CPP hash value
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addComment(txtp, fl, "Hash value to make sure this file and the corresponding");
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@ -222,33 +227,41 @@ private:
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txtp->addText(fl, "end\n\n");
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// Sequential process
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addComment(txtp, fl, "Evaluate clock edges");
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m_clkSensp = new AstTextBlock(fl, "always @(", false, true);
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txtp->addNodep(m_clkSensp);
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txtp->addText(fl, ") begin\n");
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m_comboIgnoreParamsp
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= new AstTextBlock(fl, m_libName + "_protectlib_combo_ignore(\n", false, true);
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m_comboIgnoreParamsp->addText(fl, "handle__V\n");
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txtp->addNodep(m_comboIgnoreParamsp);
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txtp->addText(fl, ");\n");
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m_seqParamsp = new AstTextBlock(
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fl, "last_seq_seqnum__V <= " + m_libName + "_protectlib_seq_update(\n", false, true);
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m_seqParamsp->addText(fl, "handle__V\n");
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txtp->addNodep(m_seqParamsp);
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txtp->addText(fl, ");\n");
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m_nbAssignsp = new AstTextBlock(fl);
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txtp->addNodep(m_nbAssignsp);
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txtp->addText(fl, "end\n\n");
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if (m_hasClk) {
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addComment(txtp, fl, "Evaluate clock edges");
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m_clkSensp = new AstTextBlock(fl, "always @(", false, true);
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txtp->addNodep(m_clkSensp);
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txtp->addText(fl, ") begin\n");
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m_comboIgnoreParamsp
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= new AstTextBlock(fl, m_libName + "_protectlib_combo_ignore(\n", false, true);
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m_comboIgnoreParamsp->addText(fl, "handle__V\n");
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txtp->addNodep(m_comboIgnoreParamsp);
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txtp->addText(fl, ");\n");
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m_seqParamsp = new AstTextBlock(
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fl, "last_seq_seqnum__V <= " + m_libName + "_protectlib_seq_update(\n", false,
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true);
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m_seqParamsp->addText(fl, "handle__V\n");
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txtp->addNodep(m_seqParamsp);
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txtp->addText(fl, ");\n");
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m_nbAssignsp = new AstTextBlock(fl);
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txtp->addNodep(m_nbAssignsp);
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txtp->addText(fl, "end\n\n");
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}
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// Select between combinatorial and sequential results
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addComment(txtp, fl, "Select between combinatorial and sequential results");
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txtp->addText(fl, "always @(*) begin\n");
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m_seqAssignsp = new AstTextBlock(fl, "if (last_seq_seqnum__V > "
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"last_combo_seqnum__V) begin\n");
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txtp->addNodep(m_seqAssignsp);
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m_comboAssignsp = new AstTextBlock(fl, "end else begin\n");
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txtp->addNodep(m_comboAssignsp);
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txtp->addText(fl, "end\n");
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if (m_hasClk) {
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m_seqAssignsp = new AstTextBlock(fl, "if (last_seq_seqnum__V > "
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"last_combo_seqnum__V) begin\n");
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txtp->addNodep(m_seqAssignsp);
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m_comboAssignsp = new AstTextBlock(fl, "end else begin\n");
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txtp->addNodep(m_comboAssignsp);
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txtp->addText(fl, "end\n");
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} else {
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m_comboAssignsp = new AstTextBlock(fl, "");
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txtp->addNodep(m_comboAssignsp);
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}
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txtp->addText(fl, "end\n\n");
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// Final
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@ -327,19 +340,21 @@ private:
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txtp->addText(fl, "return handlep__V->m_seqnum++;\n");
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txtp->addText(fl, "}\n\n");
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seqComment(txtp, fl);
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m_cSeqParamsp = new AstTextBlock(
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fl, "long long " + m_libName + "_protectlib_seq_update(\n", false, true);
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m_cSeqParamsp->addText(fl, "void* vhandlep__V\n");
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txtp->addNodep(m_cSeqParamsp);
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txtp->addText(fl, ")\n");
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m_cSeqClksp = new AstTextBlock(fl, "{\n");
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castPtr(fl, m_cSeqClksp);
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txtp->addNodep(m_cSeqClksp);
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m_cSeqOutsp = new AstTextBlock(fl, "handlep__V->eval();\n");
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txtp->addNodep(m_cSeqOutsp);
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txtp->addText(fl, "return handlep__V->m_seqnum++;\n");
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txtp->addText(fl, "}\n\n");
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if (m_hasClk) {
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seqComment(txtp, fl);
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m_cSeqParamsp = new AstTextBlock(
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fl, "long long " + m_libName + "_protectlib_seq_update(\n", false, true);
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m_cSeqParamsp->addText(fl, "void* vhandlep__V\n");
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txtp->addNodep(m_cSeqParamsp);
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txtp->addText(fl, ")\n");
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m_cSeqClksp = new AstTextBlock(fl, "{\n");
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castPtr(fl, m_cSeqClksp);
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txtp->addNodep(m_cSeqClksp);
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m_cSeqOutsp = new AstTextBlock(fl, "handlep__V->eval();\n");
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txtp->addNodep(m_cSeqOutsp);
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txtp->addText(fl, "return handlep__V->m_seqnum++;\n");
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txtp->addText(fl, "}\n\n");
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}
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comboIgnoreComment(txtp, fl);
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m_cIgnoreParamsp = new AstTextBlock(
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@ -369,6 +384,7 @@ private:
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}
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if (nodep->direction() == VDirection::INPUT) {
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if (nodep->isUsedClock() || nodep->attrClocker() == VVarAttrClocker::CLOCKER_YES) {
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UASSERT_OBJ(m_hasClk, nodep, "checkIfClockExists() didn't find this clock");
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handleClock(nodep);
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} else {
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handleDataInput(nodep);
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@ -396,8 +412,10 @@ private:
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FileLine* fl = varp->fileline();
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handleInput(varp);
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m_seqPortsp->addNodep(varp->cloneTree(false));
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m_seqParamsp->addText(fl, varp->name() + "\n");
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m_clkSensp->addText(fl, "edge(" + varp->name() + ")");
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if (m_hasClk) {
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m_seqParamsp->addText(fl, varp->name() + "\n");
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m_clkSensp->addText(fl, "edge(" + varp->name() + ")");
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}
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m_cSeqParamsp->addText(fl, varp->dpiArgType(true, false) + "\n");
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m_cSeqClksp->addText(fl, cInputConnection(varp));
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}
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@ -408,7 +426,7 @@ private:
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m_comboPortsp->addNodep(varp->cloneTree(false));
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m_comboParamsp->addText(fl, varp->name() + "\n");
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m_comboIgnorePortsp->addNodep(varp->cloneTree(false));
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m_comboIgnoreParamsp->addText(fl, varp->name() + "\n");
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if (m_hasClk) { m_comboIgnoreParamsp->addText(fl, varp->name() + "\n"); }
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m_cComboParamsp->addText(fl, varp->dpiArgType(true, false) + "\n");
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m_cComboInsp->addText(fl, cInputConnection(varp));
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m_cIgnoreParamsp->addText(fl, varp->dpiArgType(true, false) + "\n");
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@ -421,29 +439,49 @@ private:
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m_modPortsp->addNodep(varp->cloneTree(false));
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m_comboPortsp->addNodep(varp->cloneTree(false));
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m_comboParamsp->addText(fl, varp->name() + "_combo__V\n");
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m_seqPortsp->addNodep(varp->cloneTree(false));
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m_seqParamsp->addText(fl, varp->name() + "_tmp__V\n");
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if (m_hasClk) {
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m_seqPortsp->addNodep(varp->cloneTree(false));
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m_seqParamsp->addText(fl, varp->name() + "_tmp__V\n");
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}
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AstNodeDType* comboDtypep = varp->dtypep()->cloneTree(false);
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m_comboDeclsp->addNodep(comboDtypep);
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m_comboDeclsp->addText(fl, " " + varp->name() + "_combo__V;\n");
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AstNodeDType* seqDtypep = varp->dtypep()->cloneTree(false);
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m_seqDeclsp->addNodep(seqDtypep);
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m_seqDeclsp->addText(fl, " " + varp->name() + "_seq__V;\n");
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if (m_hasClk) {
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AstNodeDType* seqDtypep = varp->dtypep()->cloneTree(false);
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m_seqDeclsp->addNodep(seqDtypep);
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m_seqDeclsp->addText(fl, " " + varp->name() + "_seq__V;\n");
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AstNodeDType* tmpDtypep = varp->dtypep()->cloneTree(false);
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m_tmpDeclsp->addNodep(tmpDtypep);
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m_tmpDeclsp->addText(fl, " " + varp->name() + "_tmp__V;\n");
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AstNodeDType* tmpDtypep = varp->dtypep()->cloneTree(false);
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m_tmpDeclsp->addNodep(tmpDtypep);
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m_tmpDeclsp->addText(fl, " " + varp->name() + "_tmp__V;\n");
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m_nbAssignsp->addText(fl, varp->name() + "_seq__V <= " + varp->name() + "_tmp__V;\n");
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m_seqAssignsp->addText(fl, varp->name() + " = " + varp->name() + "_seq__V;\n");
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m_nbAssignsp->addText(fl, varp->name() + "_seq__V <= " + varp->name() + "_tmp__V;\n");
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m_seqAssignsp->addText(fl, varp->name() + " = " + varp->name() + "_seq__V;\n");
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}
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m_comboAssignsp->addText(fl, varp->name() + " = " + varp->name() + "_combo__V;\n");
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m_cComboParamsp->addText(fl, varp->dpiArgType(true, false) + "\n");
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m_cComboOutsp->addText(fl,
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V3Task::assignInternalToDpi(varp, true, "", "", "handlep__V->"));
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m_cSeqParamsp->addText(fl, varp->dpiArgType(true, false) + "\n");
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m_cSeqOutsp->addText(fl, V3Task::assignInternalToDpi(varp, true, "", "", "handlep__V->"));
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if (m_hasClk) {
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m_cSeqParamsp->addText(fl, varp->dpiArgType(true, false) + "\n");
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m_cSeqOutsp->addText(fl,
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V3Task::assignInternalToDpi(varp, true, "", "", "handlep__V->"));
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}
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}
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static bool checkIfClockExists(AstNodeModule* modp) {
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for (AstNode* stmtp = modp->stmtsp(); stmtp; stmtp = stmtp->nextp()) {
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if (AstVar* varp = VN_CAST(stmtp, Var)) {
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if (varp->direction() == VDirection::INPUT
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&& (varp->isUsedClock()
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|| varp->attrClocker() == VVarAttrClocker::CLOCKER_YES)) {
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return true;
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}
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}
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}
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return false;
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}
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public:
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@ -475,7 +513,8 @@ public:
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, m_cIgnoreParamsp(NULL)
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, m_libName(v3Global.opt.protectLib())
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, m_topName(v3Global.opt.prefix())
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, m_foundTop(false) {
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, m_foundTop(false)
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, m_hasClk(false) {
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iterate(nodep);
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}
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};
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69
test_regress/t/t_prot_lib_comb.pl
Executable file
69
test_regress/t/t_prot_lib_comb.pl
Executable file
@ -0,0 +1,69 @@
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#!/usr/bin/env perl
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# Makes the test run with tracing enabled by default, can be overridden
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# with --notrace
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unshift(@ARGV, "--trace");
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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2019 by Todd Strader. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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scenarios(
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vlt => 1,
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xsim => 1,
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);
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$Self->{sim_time} = $Self->{benchmark} * 100 if $Self->{benchmark};
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my $secret_prefix = "secret";
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my $secret_dir = "$Self->{obj_dir}/$secret_prefix";
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mkdir $secret_dir;
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while (1) {
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# Always compile the secret file with Verilator no matter what simulator
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# we are testing with
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run(logfile => "$secret_dir/vlt_compile.log",
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cmd => ["perl",
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"$ENV{VERILATOR_ROOT}/bin/verilator",
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"--prefix",
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"Vt_prot_lib_secret",
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"-cc",
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"-Mdir",
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$secret_dir,
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"--protect-lib",
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$secret_prefix,
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"t/t_prot_lib_comb.v"],
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verilator_run => 1,
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);
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last if $Self->{errors};
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run(logfile => "$secret_dir/secret_gcc.log",
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cmd=>[$ENV{MAKE},
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"-C",
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$secret_dir,
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"-f",
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"Vt_prot_lib_secret.mk"]);
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last if $Self->{errors};
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compile(
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verilator_flags2 => ["$secret_dir/secret.sv",
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"+define+PROCESS_TOP",
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"-LDFLAGS",
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"$secret_prefix/libsecret.a"],
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xsim_flags2 => ["$secret_dir/secret.sv"],
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);
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execute(
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check_finished => 1,
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xsim_run_flags2 => ["--sv_lib",
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"$secret_dir/libsecret",
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"--dpi_absolute"],
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);
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ok(1);
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last;
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}
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1;
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56
test_regress/t/t_prot_lib_comb.v
Normal file
56
test_regress/t/t_prot_lib_comb.v
Normal file
@ -0,0 +1,56 @@
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// DESCRIPTION: Verilator: Verilog Test module
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2020 by Yutetsu TAKATSUKASA.
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// SPDX-License-Identifier: CC0-1.0
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`ifdef PROCESS_TOP
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`define CHECK if (out0 != (in0 ^ in1) || out1 != (in0 | in1) || out2 != (in0 & in1)) begin \
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$display("Mismatch in0:%b in1:%b out0:%b out1:%b out2:%b", in0, in1, out0, out1, out2); \
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$stop; \
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end
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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logic in0, in1;
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logic out0, out1, out2;
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logic [31:0] count = 0;
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// actually XOR and OR and AND
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secret i_secret(.in0(in0), .in1(in1), .out0(out0), .out1(out1), .out2(out2));
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always @(posedge clk) begin
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count <= count + 32'd1;
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if (count == 32'd1) begin
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in0 <= 1'b0;
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in1 <= 1'b0;
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end else if (count == 32'd2) begin
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`CHECK
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in0 <= 1'b1;
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in1 <= 1'b0;
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end else if (count == 32'd3) begin
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`CHECK
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in0 <= 1'b0;
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in1 <= 1'b1;
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end else if (count == 32'd4) begin
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`CHECK
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in0 <= 1'b1;
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in1 <= 1'b1;
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end else if (count == 32'd5) begin
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`CHECK
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$write("*-* All Finished *-*\n");
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$finish;
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end
|
||||
end
|
||||
endmodule
|
||||
|
||||
`else
|
||||
module secret(input in0, input in1, output out0, output out1, output out2);
|
||||
assign out0 = in0 ^ in1;
|
||||
assign out1 = in0 | in1;
|
||||
assign out2 = in0 & in1;
|
||||
endmodule
|
||||
`endif
|
||||
Loading…
Reference in New Issue
Block a user