Add --valgrind switch (#4828)

bin/verilator

@@ -32,6 +32,7 @@ my $opt_rr;
 my $opt_gdbbt;
 my $opt_quiet_exit;
 my $opt_unlimited_stack = 1;
+my $opt_valgrind;
 
 # No arguments can't do anything useful.  Give help
 if ($#ARGV < 0) {
@@ -59,6 +60,7 @@ if (! GetOptions(
           "quiet-exit!"      => \$opt_quiet_exit,
           "rr!"              => \$opt_rr,
           "unlimited-stack!" => \$opt_unlimited_stack,
+          "valgrind!"        => \$opt_valgrind,
           # Additional parameters
           "<>"               => sub {},      # Ignored
     )) {
@@ -109,6 +111,18 @@ if ($opt_gdb) {
          . " -ex \"run " . join(' ', @quoted_sw)."\""
          . " -ex 'set width 0'"
          . " -ex 'bt' -ex 'quit'");
+} elsif ($opt_valgrind) {
+    # Run under valgrind
+    my $valgrind_bin = ($ENV{VERILATOR_VALGRIND} || "valgrind --error-exitcode=1 --max-stackframe=2815880"
+        # Magic number sugested by valgrind, may need to be increased in future
+        # if you get warnings. See: https://valgrind.org/docs/manual/manual-core.html#opt.max-stackframe
+        );
+
+    run (ulimit_stack_unlimited()
+         . aslr_off()
+         . $valgrind_bin
+         . " " . verilator_bin()
+         . " " . join(' ', @quoted_sw));
 } elsif ($Debug) {
     # Debug
     run(ulimit_stack_unlimited()
@@ -453,6 +467,7 @@ detailed descriptions of these arguments.
     --unused-regexp <regexp>    Tune UNUSED lint signals
      -V                         Verbose version and config
      -v <filename>              Verilog library
+    --valgrind                  Run Verilator under valgrind
     --verilate-jobs             Job threads for Verilation stage
     --no-verilate               Skip Verilation and just compile previously Verilated code
      +verilog1995ext+<ext>      Synonym for +1364-1995ext+<ext>

docs/guide/environment.rst

@@ -118,6 +118,11 @@ associated programs.
 
    See :ref:`Installation` for more details.
 
+.. option:: VERILATOR_VALGRIND
+
+   If set, the command to run when using the :vlopt:`--valgrind` option, such as
+   "valgrind --tool=callgrind".  If not specified, it will use "valgrind".
+
 
 Make Variables
 ==============

docs/guide/exe_verilator.rst

@@ -1516,6 +1516,11 @@ Summary:
    used to resolve instances in the top-level module, otherwise, they are
    ignored.  Note "-v" is relatively standard across Verilog tools.
 
+.. option:: --valgrind
+
+   Run Verilator under `Valgrind <https://valgrind.org/>`_.  The command may be
+   changed with :option:`VERILATOR_VALGRIND`.
+
 .. option:: --no-verilate
 
    When using :vlopt:`--build`, disable the generation of C++/SystemC code, and

docs/internals.rst

@@ -1937,6 +1937,9 @@ driver.pl Non-Scenario Arguments
 --trace
   Set the simulator specific flags to request waveform tracing.
 
+--valgrind
+  Same as ``verilator --valgrind``: Run Verilator under `Valgrind <https://valgrind.org/>`_.
+
 --verbose
   Compile and run the test in verbose mode. This means ``TEST_VERBOSE``
   will be defined for the test (Verilog and any C++/SystemC wrapper).

src/V3Options.cpp

@@ -1539,6 +1539,7 @@ void V3Options::parseOptsList(FileLine* fl, const string& optdir, int argc,
     DECL_OPTION("-v", CbVal, [this, &optdir](const char* valp) {
         V3Options::addLibraryFile(parseFileArg(optdir, valp));
     });
+    DECL_OPTION("-valgrind", CbCall, []() {});  // Processed only in bin/verilator shell
     DECL_OPTION("-verilate-jobs", CbVal, [this, fl](const char* valp) {
         int val = std::atoi(valp);
         if (val < 0) {

test_regress/driver.pl

@@ -1765,6 +1765,7 @@ sub _run {
                 $wholefile =~ s/^- [^\n]+\n//mig;
                 $wholefile =~ s/^- [a-z.0-9]+:\d+:[^\n]+\n//mig;
                 $wholefile =~ s/^dot [^\n]+\n//mig;
+                $wholefile =~ s/^==[0-9]+== [^\n]+\n//mig; # valgrind
 
                 # Compare
                 my $quoted = quotemeta($param{expect});
@@ -2277,6 +2278,7 @@ sub files_identical {
                     && !/^libgcov.*/
                     && !/--- \/tmp\//  # t_difftree.pl
                     && !/\+\+\+ \/tmp\//  # t_difftree.pl
+                    && !/^==[0-9]+== ?[^\n]*\n/  # valgrind
             } @l1;
             @l1 = map {
                 while (s/(Internal Error: [^\n]+\.(cpp|h)):[0-9]+/$1:#/g) {}

test_regress/t/t_flag_help_valgrind.pl

@@ -0,0 +1,18 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+run(fails => 0,
+    cmd => ["../bin/verilator", "--help", "--valgrind"],
+    tee => 0,
+    verilator_run => 1,
+    );
+
+ok(1);
+1;