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This commit is contained in:
Wilson Snyder 2021-02-16 22:40:21 -05:00
parent 2b2fe13e79
commit c5e5be8e99
2 changed files with 2 additions and 2 deletions
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2
test_regress/t/t_EXAMPLE.pl
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@ -2,7 +2,7 @@
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2019 by Wilson Snyder. This program is free software; you
# Copyright 2021 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.

2
test_regress/t/t_EXAMPLE.v
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@ -13,7 +13,7 @@
// please note it here, otherwise:**
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2020 by ____YOUR_NAME_HERE____.
// any use, without warranty, 2021 by ____YOUR_NAME_HERE____.
// SPDX-License-Identifier: CC0-1.0
module t(/*AUTOARG*/