Fix VL_STREAML_FAST_QQI with 64 bit left-hand-side (#3232) (#3235)

docs/CONTRIBUTORS

@@ -3,6 +3,7 @@ under the Developer Certificate of Origin (https://developercertificate.org/).
 
 Please see the Verilator manual for 200+ additional contributors. Thanks to all.
 
+Adrien Le Masle
 Ahmed El-Mahmoudy
 Alex Chadwick
 Àlex Torregrosa

include/verilated_funcs.h

@@ -1430,7 +1430,7 @@ static inline QData VL_STREAML_FAST_QQI(int lbits, QData ld, IData rd_log2) VL_P
     if (rd_log2) {
         const vluint32_t lbitsFloor = lbits & ~VL_MASK_I(rd_log2);
         const vluint32_t lbitsRem = lbits - lbitsFloor;
-        const QData msbMask = VL_MASK_Q(lbitsRem) << lbitsFloor;
+        const QData msbMask = lbitsFloor == 64 ? 0ULL : VL_MASK_Q(lbitsRem) << lbitsFloor;
         ret = (ret & ~msbMask) | ((ret & msbMask) << ((1ULL << rd_log2) - lbitsRem));
     }
     switch (rd_log2) {

test_regress/t/t_stream4.pl

@@ -0,0 +1,21 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(simulator => 1);
+
+compile(
+    );
+
+execute(
+    check_finished => 1,
+    );
+
+ok(1);
+1;

test_regress/t/t_stream4.v

@@ -0,0 +1,42 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2021 by Adrien Le Masle.
+// SPDX-License-Identifier: CC0-1.0
+
+//module t;
+module t (/*AUTOARG*/
+   // Inputs
+   clk
+   );
+
+   input clk;
+   integer cyc; initial cyc=1;
+
+   logic [63:0] din;
+   logic [63:0] dout;
+
+   always_comb begin
+      dout = {<<8{din}};
+   end
+
+   always @(posedge clk) begin
+      if (cyc != 0) begin
+         cyc <= cyc + 1;
+
+         if (cyc == 1) begin
+            din <= 64'h1122334455667788;
+         end
+
+         if (cyc == 2) begin
+            if (dout != 64'h8877665544332211) $stop;
+         end
+
+         if (cyc == 3) begin
+            $write("*-* All Finished *-*\n");
+            $finish;
+         end
+      end
+   end
+
+endmodule