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Add --no-decoration to remove output comments, msg2015.
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Changes
@ -6,6 +6,8 @@ indicates the contributor was also the author of the fix; Thanks!
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* Verilator 3.887 devel
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*** Add --no-decoration to remove output comments, msg2015. [Frederic Requin]
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**** Add error on DPI functions > 32 bits, msg1995. [Elliot Mednick]
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**** Fix SystemC compiles with VPI, bug1081. [Arthur Kahlich]
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@ -300,6 +300,7 @@ descriptions in the next sections for more information.
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--Mdir <directory> Name of output object directory
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--mod-prefix <topname> Name to prepend to lower classes
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--no-clk <signal-name> Prevent marking specified signal as clock
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--no-decoration Disable comments and symbol decorations
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--no-pins64 Don't use vluint64_t's for 33-64 bit sigs
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--no-skip-identical Disable skipping identical output
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+notimingchecks Ignored
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@ -843,6 +844,13 @@ the same as --prefix.
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Prevent the specified signal from being marked as clock. See C<--clk>.
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=item --no-decoration
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When creating output Verilated code, minimize comments, whitespace, symbol
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names and other decorative items, at the cost of greatly reduced
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readability. This may assist C++ compile times. This will not typically
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change the ultimate model's performance, but may in some cases.
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=item --no-pins64
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Backward compatible alias for "--pins-bv 33".
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@ -113,7 +113,7 @@ public:
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}
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if (AstEnumDType* adtypep = nodep->dtypep()->skipRefToEnump()->castEnumDType()) {
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if (adtypep->width()>64) {
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puts("// enum "+nodep->name()+" // Ignored: Too wide for C++\n");
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putsDecoration("// enum "+nodep->name()+" // Ignored: Too wide for C++\n");
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} else {
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puts("enum "+nodep->name()+" {\n");
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for (AstEnumItem* itemp = adtypep->itemsp(); itemp; itemp=itemp->nextp()->castEnumItem()) {
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@ -220,7 +220,7 @@ public:
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nodep->v3fatalSrc("Case statements should have been reduced out\n");
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}
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virtual void visit(AstComment* nodep, AstNUser*) {
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puts((string)"// "+nodep->name()+" at "+nodep->fileline()->ascii()+"\n");
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putsDecoration((string)"// "+nodep->name()+" at "+nodep->fileline()->ascii()+"\n");
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nodep->iterateChildren(*this);
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}
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virtual void visit(AstCoverDecl* nodep, AstNUser*) {
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@ -499,13 +499,13 @@ public:
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nodep->bodysp()->iterateAndNext(*this);
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}
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virtual void visit(AstUCStmt* nodep, AstNUser*) {
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puts("// $c statement at "+nodep->fileline()->ascii()+"\n");
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putsDecoration("// $c statement at "+nodep->fileline()->ascii()+"\n");
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nodep->bodysp()->iterateAndNext(*this);
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puts("\n");
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}
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virtual void visit(AstUCFunc* nodep, AstNUser*) {
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puts("\n");
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puts("// $c function at "+nodep->fileline()->ascii()+"\n");
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putsDecoration("// $c function at "+nodep->fileline()->ascii()+"\n");
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nodep->bodysp()->iterateAndNext(*this);
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puts("\n");
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}
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@ -844,7 +844,7 @@ class EmitCImp : EmitCStmts {
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if (nodep->symProlog()) puts(EmitCBaseVisitor::symTopAssign()+"\n");
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if (nodep->initsp()) puts("// Variables\n");
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if (nodep->initsp()) putsDecoration("// Variables\n");
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ofp()->putAlign(V3OutFile::AL_AUTO, 4);
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for (AstNode* subnodep=nodep->argsp(); subnodep; subnodep = subnodep->nextp()) {
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if (AstVar* varp=subnodep->castVar()) {
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@ -858,11 +858,11 @@ class EmitCImp : EmitCStmts {
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nodep->initsp()->iterateAndNext(*this);
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if (nodep->stmtsp()) puts("// Body\n");
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if (nodep->stmtsp()) putsDecoration("// Body\n");
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nodep->stmtsp()->iterateAndNext(*this);
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if (!m_blkChangeDetVec.empty()) emitChangeDet();
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if (nodep->finalsp()) puts("// Final\n");
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if (nodep->finalsp()) putsDecoration("// Final\n");
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nodep->finalsp()->iterateAndNext(*this);
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//
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@ -873,7 +873,7 @@ class EmitCImp : EmitCStmts {
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}
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void emitChangeDet() {
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puts("// Change detection\n");
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putsDecoration("// Change detection\n");
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puts("QData __req = false; // Logically a bool\n"); // But not because it results in faster code
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bool gotOne = false;
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for (vector<AstChangeDet*>::iterator it = m_blkChangeDetVec.begin();
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@ -1474,7 +1474,7 @@ void EmitCImp::emitVarReset(AstVar* varp) {
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void EmitCImp::emitCoverageDecl(AstNodeModule* modp) {
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if (v3Global.opt.coverage()) {
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ofp()->putsPrivate(true);
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puts("// Coverage\n");
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putsDecoration("// Coverage\n");
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puts("void __vlCoverInsert(uint32_t* countp, bool enable, const char* filenamep, int lineno, int column,\n");
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puts( "const char* hierp, const char* pagep, const char* commentp);\n");
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}
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@ -1494,12 +1494,12 @@ void EmitCImp::emitCtorImp(AstNodeModule* modp) {
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emitCellCtors(modp);
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emitSensitives();
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puts("// Reset internal values\n");
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putsDecoration("// Reset internal values\n");
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if (modp->isTop()) {
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if (v3Global.opt.inhibitSim()) puts("__Vm_inhibitSim = false;\n");
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puts("\n");
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}
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puts("// Reset structure values\n");
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putsDecoration("// Reset structure values\n");
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puts("_ctor_var_reset();\n");
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emitTextSection(AstType::atSCCTOR);
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if (optSystemPerl()) puts("SP_AUTO_CTOR;\n");
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@ -1515,7 +1515,7 @@ void EmitCImp::emitConfigureImp(AstNodeModule* modp) {
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if (nodep->castCoverDecl()) {
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if (first) {
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first = false;
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puts("// Coverage Declarations\n");
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putsDecoration("// Coverage Declarations\n");
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}
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nodep->accept(*this);
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splitSizeInc(nodep);
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@ -1681,7 +1681,7 @@ void EmitCImp::emitSensitives() {
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// Create sensitivity list for when to evaluate the model.
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// If C++ code, the user must call this routine themself.
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if (m_modp->isTop() && optSystemC()) {
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puts("// Sensitivities on all clocks and combo inputs\n");
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putsDecoration("// Sensitivities on all clocks and combo inputs\n");
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puts("SC_METHOD(eval);\n");
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for (AstNode* nodep=m_modp->stmtsp(); nodep; nodep = nodep->nextp()) {
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if (AstVar* varp = nodep->castVar()) {
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@ -1713,12 +1713,12 @@ void EmitCImp::emitWrapEval(AstNodeModule* modp) {
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puts("\nvoid "+modClassName(modp)+"::eval() {\n");
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puts(EmitCBaseVisitor::symClassVar()+" = this->__VlSymsp; // Setup global symbol table\n");
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puts(EmitCBaseVisitor::symTopAssign()+"\n");
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puts("// Initialize\n");
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putsDecoration("// Initialize\n");
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puts("if (VL_UNLIKELY(!vlSymsp->__Vm_didInit)) _eval_initial_loop(vlSymsp);\n");
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if (v3Global.opt.inhibitSim()) {
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puts("if (VL_UNLIKELY(__Vm_inhibitSim)) return;\n");
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}
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puts("// Evaluate till stable\n");
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putsDecoration("// Evaluate till stable\n");
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puts("VL_DEBUG_IF(VL_PRINTF(\"\\n----TOP Evaluate "+modClassName(modp)+"::eval\\n\"); );\n");
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puts("int __VclockLoop = 0;\n");
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puts("QData __Vchange=1;\n");
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@ -1887,7 +1887,7 @@ void EmitCImp::emitInt(AstNodeModule* modp) {
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if (optSystemPerl()) {
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puts("/*AUTOSUBCELLS*/\n\n");
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} else {
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puts("// CELLS\n");
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putsDecoration("// CELLS\n");
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if (modp->isTop()) puts("// Public to allow access to /*verilator_public*/ items;\n");
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if (modp->isTop()) puts("// otherwise the application code can consider these internals.\n");
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for (AstNode* nodep=modp->stmtsp(); nodep; nodep = nodep->nextp()) {
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@ -1939,9 +1939,9 @@ void EmitCImp::emitInt(AstNodeModule* modp) {
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// These should be static const values, however microsloth VC++ doesn't
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// support them. They also cause problems with GDB under GCC2.95.
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if (varp->isWide()) { // Unsupported for output
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puts("// enum WData "+varp->name()+" //wide");
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putsDecoration("// enum WData "+varp->name()+" //wide");
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} else if (!varp->valuep()->castConst()) { // Unsupported for output
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//puts("// enum ..... "+varp->name()+" //not simple value, see variable above instead");
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//putsDecoration("// enum ..... "+varp->name()+" //not simple value, see variable above instead");
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} else {
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puts("enum ");
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puts(varp->isQuad()?"_QData":"_IData");
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@ -2222,7 +2222,7 @@ class EmitCTrace : EmitCStmts {
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puts("void "+topClassName()+"::traceInit("
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+v3Global.opt.traceClassBase()+"* vcdp, void* userthis, uint32_t code) {\n");
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puts("// Callback from vcd->open()\n");
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putsDecoration("// Callback from vcd->open()\n");
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puts(topClassName()+"* t=("+topClassName()+"*)userthis;\n");
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puts(EmitCBaseVisitor::symClassVar()+" = t->__VlSymsp; // Setup global symbol table\n");
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puts("if (!Verilated::calcUnusedSigs()) vl_fatal(__FILE__,__LINE__,__FILE__,\"Turning on wave traces requires Verilated::traceEverOn(true) call before time 0.\");\n");
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@ -2235,7 +2235,7 @@ class EmitCTrace : EmitCStmts {
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puts("void "+topClassName()+"::traceFull("
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+v3Global.opt.traceClassBase()+"* vcdp, void* userthis, uint32_t code) {\n");
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puts("// Callback from vcd->dump()\n");
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putsDecoration("// Callback from vcd->dump()\n");
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puts(topClassName()+"* t=("+topClassName()+"*)userthis;\n");
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puts(EmitCBaseVisitor::symClassVar()+" = t->__VlSymsp; // Setup global symbol table\n");
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puts("t->traceFullThis (vlSymsp, vcdp, code);\n");
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@ -2250,7 +2250,7 @@ class EmitCTrace : EmitCStmts {
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puts("void "+topClassName()+"::traceChg("
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+v3Global.opt.traceClassBase()+"* vcdp, void* userthis, uint32_t code) {\n");
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puts("// Callback from vcd->dump()\n");
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putsDecoration("// Callback from vcd->dump()\n");
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puts(topClassName()+"* t=("+topClassName()+"*)userthis;\n");
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puts(EmitCBaseVisitor::symClassVar()+" = t->__VlSymsp; // Setup global symbol table\n");
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puts("if (vlSymsp->getClearActivity()) {\n");
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@ -2404,16 +2404,16 @@ class EmitCTrace : EmitCStmts {
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} else if (nodep->funcType() == AstCFuncType::TRACE_CHANGE_SUB) {
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} else nodep->v3fatalSrc("Bad Case");
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if (nodep->initsp()) puts("// Variables\n");
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if (nodep->initsp()) putsDecoration("// Variables\n");
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emitVarList(nodep->initsp(), EVL_ALL, "");
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nodep->initsp()->iterateAndNext(*this);
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ofp()->putAlign(V3OutFile::AL_AUTO, 4);
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puts("// Body\n");
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putsDecoration("// Body\n");
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puts("{\n");
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nodep->stmtsp()->iterateAndNext(*this);
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puts("}\n");
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if (nodep->finalsp()) puts("// Final\n");
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if (nodep->finalsp()) putsDecoration("// Final\n");
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nodep->finalsp()->iterateAndNext(*this);
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puts("}\n");
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}
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V3OutCFile* ofp() const { return m_ofp; }
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void puts(const string& str) { ofp()->puts(str); }
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void putbs(const string& str) { ofp()->putbs(str); }
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void putsDecoration(const string& str) { if (v3Global.opt.decoration()) puts(str); }
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void putsQuoted(const string& str) { ofp()->putsQuoted(str); }
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bool optSystemC() { return v3Global.opt.systemC(); }
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bool optSystemPerl() { return v3Global.opt.systemPerl(); }
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@ -689,6 +689,7 @@ void V3Options::parseOptsList(FileLine* fl, const string& optdir, int argc, char
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else if ( onoff (sw, "-debug-check", flag/*ref*/) ){ m_debugCheck = flag; }
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else if ( !strcmp (sw, "-debug-sigsegv") ) { throwSigsegv(); } // Undocumented, see also --debug-abort
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else if ( !strcmp (sw, "-debug-fatalsrc") ) { v3fatalSrc("--debug-fatal-src"); } // Undocumented, see also --debug-abort
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else if ( onoff (sw, "-decoration", flag/*ref*/) ) { m_decoration = flag; }
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else if ( onoff (sw, "-dump-tree", flag/*ref*/) ) { m_dumpTree = flag ? 3 : 0; } // Also see --dump-treei
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else if ( onoff (sw, "-exe", flag/*ref*/) ) { m_exe = flag; }
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else if ( onoff (sw, "-ignc", flag/*ref*/) ) { m_ignc = flag; }
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@ -1199,6 +1200,7 @@ V3Options::V3Options() {
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m_coverageUnderscore = false;
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m_coverageUser = false;
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m_debugCheck = false;
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m_decoration = true;
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m_exe = false;
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m_ignc = false;
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m_inhibitSim = false;
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@ -75,6 +75,7 @@ class V3Options {
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bool m_coverageUnderscore;// main switch: --coverage-underscore
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bool m_coverageUser; // main switch: --coverage-func
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bool m_debugCheck; // main switch: --debug-check
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bool m_decoration; // main switch: --decoration
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bool m_exe; // main switch: --exe
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bool m_ignc; // main switch: --ignc
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bool m_inhibitSim; // main switch: --inhibit-sim
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@ -226,6 +227,7 @@ class V3Options {
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bool coverageUnderscore() const { return m_coverageUnderscore; }
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bool coverageUser() const { return m_coverageUser; }
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bool debugCheck() const { return m_debugCheck; }
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bool decoration() const { return m_decoration; }
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bool exe() const { return m_exe; }
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bool trace() const { return m_trace; }
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bool traceDups() const { return m_traceDups; }
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21
test_regress/t/t_trace_decoration.pl
Executable file
21
test_regress/t/t_trace_decoration.pl
Executable file
@ -0,0 +1,21 @@
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#!/usr/bin/perl
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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can
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# redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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compile (
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verilator_flags2 => ['--cc --trace --no-decoration'],
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);
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execute (
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check_finished=>1,
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);
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file_grep_not ("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr!// Body!x);
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ok(1);
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1;
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test_regress/t/t_trace_decoration.v
Normal file
22
test_regress/t/t_trace_decoration.v
Normal file
@ -0,0 +1,22 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2014 by Wilson Snyder.
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module t (clk);
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input clk;
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integer a_very_long_name_which_we_will_hash_eventually=0;
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always @ (posedge clk) begin
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a_very_long_name_which_we_will_hash_eventually <= a_very_long_name_which_we_will_hash_eventually + 1;
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if (a_very_long_name_which_we_will_hash_eventually == 5) begin
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fin();
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end
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end
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task fin;
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$write("*-* All Finished *-*\n");
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$finish;
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endtask
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endmodule
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