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Match up with Verilog-Perl: add specify operators

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git-svn-id: file://localhost/svn/verilator/trunk/verilator@956 77ca24e4-aefa-0310-84f0-b9a241c72d87
This commit is contained in:
Wilson Snyder 2007-10-18 16:29:19 +00:00
parent 9ac0f1accb
commit c300ab6dd9
2 changed files with 15 additions and 0 deletions
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6
src/verilog.l
View File

@ -568,6 +568,12 @@ escid \\[^ \t\f\r\n]+
"~&" {yylval.fileline = CRELINE(); return yP_NAND;}
"~|" {yylval.fileline = CRELINE(); return yP_NOR;}
"->" {yylval.fileline = CRELINE(); return yP_MINUSGT;}
"=>" {yylval.fileline = CRELINE(); return yP_EQGT; }
"*>" {yylval.fileline = CRELINE(); return yP_ASTGT; }
"+=>" {yylval.fileline = CRELINE(); return yP_PLUSEQGT; }
"+*>" {yylval.fileline = CRELINE(); return yP_PLUSASTGT; }
"-=>" {yylval.fileline = CRELINE(); return yP_MINUSEQGT; }
"-*>" {yylval.fileline = CRELINE(); return yP_MINUSASTGT; }
}
/* Verilog 2001 Operators */

9
src/verilog.y
View File

@ -248,6 +248,12 @@ class AstSenTree;
%token<fileline> yP_PLUSCOLON "+:"
%token<fileline> yP_MINUSCOLON "-:"
%token<fileline> yP_EQGT "=>"
%token<fileline> yP_ASTGT "*>"
%token<fileline> yP_PLUSEQGT "+=>"
%token<fileline> yP_PLUSASTGT "+*>"
%token<fileline> yP_MINUSEQGT "-=>"
%token<fileline> yP_MINUSASTGT "-*>"
%token<fileline> yPSL_BRA "{"
%token<fileline> yPSL_KET "}"
@ -1132,6 +1138,9 @@ specifyJunk: dlyTerm {} /* ignored */
| yPSL_KET {}
| yP_OR_MINUS_GT {}
| yP_OR_EQ_GT {}
| yP_EQGT {} | yP_ASTGT {}
| yP_PLUSEQGT {} | yP_PLUSASTGT {}
| yP_MINUSEQGT {} | yP_MINUSASTGT {}
| error {}
;