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Add error on duplicate pattern assignments, bug1145.

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This commit is contained in:
Wilson Snyder 2017-03-23 18:15:03 -04:00
parent 8f2bc6e028
commit c27a60658f
5 changed files with 37 additions and 6 deletions
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2
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@ -9,6 +9,8 @@ The contributors that suggested a given feature are shown in []. Thanks!
** Add --relative-includes. [Rob Stoddard] ** Add --relative-includes. [Rob Stoddard]
*** Add error on duplicate pattern assignments, bug1145. [Johan Bjork]
**** Fix error on improperly widthed default function, bug984. [Todd Strader] **** Fix error on improperly widthed default function, bug984. [Todd Strader]
**** Fix 2009 localparam syntax, msg2139. [Galen Seitz] **** Fix 2009 localparam syntax, msg2139. [Galen Seitz]

7
bin/verilator
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@ -2946,13 +2946,12 @@ Simply use a different register for the flop:
always @* foo[0] = foo_flopped[0]; always @* foo[0] = foo_flopped[0];
always @* foo[1] = ... always @* foo[1] = ...
This is good coding practice anyways.
It is also possible to disable this error when one of the assignments is It is also possible to disable this error when one of the assignments is
inside a public task. inside a public task.
Ignoring this warning may make Verilator simulations differ from other This is not illegal in SystemVerilog, but a violation of good coding
simulators. practice. Verilator reports this as an error, because ignoring this warning
may make Verilator simulations differ from other simulators.
=item BLKSEQ =item BLKSEQ

5
src/V3Width.cpp
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@ -1613,7 +1613,10 @@ private:
} else if (!memp && patp) { patp->v3error("Assignment pattern contains too many elements"); } else if (!memp && patp) { patp->v3error("Assignment pattern contains too many elements");
memp=NULL; patp=NULL; break; memp=NULL; patp=NULL; break;
} else { } else {
patmap.insert(make_pair(memp, patp)); pair<PatMap::iterator, bool> ret = patmap.insert(make_pair(memp, patp));
if (!ret.second) {
patp->v3error("Assignment pattern contains duplicate entry: " << patp->keyp()->castText()->text());
}
} }
// Next // Next
if (memp) memp = memp->nextp()->castMemberDType(); if (memp) memp = memp->nextp()->castMemberDType();

6
test_regress/t/t_struct_init.v
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@ -49,6 +49,10 @@ module t;
pack2_t arr[2]; pack2_t arr[2];
`ifdef T_STRUCT_INIT_BAD
const b4_t b4_const_c = '{b1: 1'b1, b1: 1'b0, b0:1'b0, b2: 1'b1, b3: 1'b1};
`endif
initial begin initial begin
pack3_t tsu; pack3_t tsu;
tsu = 6'b110110; tsu = 6'b110110;
@ -119,5 +123,5 @@ module t;
if (in !== cmp) $stop; if (in !== cmp) $stop;
pat = 1'b0; pat = 1'b0;
endfunction endfunction
endmodule endmodule

23
test_regress/t/t_struct_init_bad.pl Executable file
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@ -0,0 +1,23 @@
#!/usr/bin/perl
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2003 by Wilson Snyder. This program is free software; you can
# redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
top_filename("t/t_struct_init.v");
compile (
v_flags2 => ['+define+T_STRUCT_INIT_BAD'],
fails => 1,
expect=>
'%Error: t/t_struct_init.v:\d+: Assignment pattern contains duplicate entry: b1
%Error: Exiting due to.*'
);
ok(1);
1;