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Fix struct redefinition (#4276)
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c3e5db5f04
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@ -27,6 +27,7 @@
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#include "V3Ast.h"
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#include "V3Global.h"
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#include "V3UniqueNames.h"
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VL_DEFINE_DEBUG_FUNCTIONS;
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@ -41,6 +42,7 @@ private:
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// MEMBERS
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string m_prefix; // String prefix to add to name based on hier
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V3UniqueNames m_names; // For unique naming of structs and unions
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AstNodeModule* m_modp = nullptr; // Current module
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AstNodeModule* m_classPackagep = nullptr; // Package moving into
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const AstScope* m_classScopep = nullptr; // Package moving scopes into
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@ -181,8 +183,8 @@ private:
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// Give struct a pointer to its package and a final name
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dtypep->editCountInc();
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dtypep->classOrPackagep(m_classPackagep ? m_classPackagep : m_modp);
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dtypep->name(dtypep->name() + (VN_IS(dtypep, UnionDType) ? "__union" : "__struct")
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+ cvtToStr(dtypep->uniqueNum()));
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dtypep->name(
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m_names.get(dtypep->name() + (VN_IS(dtypep, UnionDType) ? "__union" : "__struct")));
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for (const AstMemberDType* itemp = dtypep->membersp(); itemp;
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itemp = VN_AS(itemp->nextp(), MemberDType)) {
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21
test_regress/t/t_unpacked_struct_redef.pl
Executable file
21
test_regress/t/t_unpacked_struct_redef.pl
Executable file
@ -0,0 +1,21 @@
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#!/usr/bin/env perl
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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2023 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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scenarios(simulator => 1);
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compile(
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);
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execute(
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check_finished => 1,
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);
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ok(1);
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1;
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26
test_regress/t/t_unpacked_struct_redef.v
Normal file
26
test_regress/t/t_unpacked_struct_redef.v
Normal file
@ -0,0 +1,26 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2023 by Antmicro Ltd.
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// SPDX-License-Identifier: CC0-1.0
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class Class#(parameter WIDTH);
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typedef logic [WIDTH-1:0] word;
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typedef struct {
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word w;
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} Struct;
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endclass
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module t;
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Class#(1)::Struct s1;
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Class#(1)::Struct s2;
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Class#(2)::Struct s3;
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initial begin
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$display("%p", s1);
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$display("%p", s2);
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$display("%p", s3);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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