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Add more patterns to t_const_opt_red.v (#2792)
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Yutetsu TAKATSUKASA
GitHub
parent
22e299e78e
commit
c1b6faff6d
@ -24,19 +24,39 @@ module t(/*AUTOARG*/
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logic a3; // From test of Test.v
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logic a4; // From test of Test.v
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logic a5; // From test of Test.v
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logic a6; // From test of Test.v
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logic a7; // From test of Test.v
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logic a8; // From test of Test.v
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logic a9; // From test of Test.v
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logic a10; // From test of Test.v
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logic a11; // From test of Test.v
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logic o1; // From test of Test.v
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logic o2; // From test of Test.v
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logic o3; // From test of Test.v
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logic o4; // From test of Test.v
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logic o5; // From test of Test.v
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logic o6; // From test of Test.v
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logic o7; // From test of Test.v
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logic o8; // From test of Test.v
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logic o9; // From test of Test.v
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logic o10; // From test of Test.v
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logic o11; // From test of Test.v
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logic x1; // From test of Test.v
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logic x2; // From test of Test.v
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logic x3; // From test of Test.v
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logic x4; // From test of Test.v
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logic x5; // From test of Test.v
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logic x6; // From test of Test.v
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logic x7; // From test of Test.v
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logic x8; // From test of Test.v
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logic x9; // From test of Test.v
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logic z1; // From test of Test.v
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logic z2; // From test of Test.v
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logic z3; // From test of Test.v
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logic z4; // From test of Test.v
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logic z5; // From test of Test.v
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logic z6; // From test of Test.v
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logic z7; // From test of Test.v
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// End of automatics
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wire [31:0] i = crc[31:0];
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@ -48,37 +68,57 @@ module t(/*AUTOARG*/
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.a3 (a3),
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.a4 (a4),
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.a5 (a5),
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.a6 (a6),
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.a7 (a7),
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.a8 (a8),
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.a9 (a9),
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.a10 (a10),
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.a11 (a11),
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.o1 (o1),
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.o2 (o2),
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.o3 (o3),
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.o4 (o4),
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.o5 (o5),
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.o6 (o6),
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.o7 (o7),
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.o8 (o8),
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.o9 (o9),
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.o10 (o10),
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.o11 (o11),
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.x1 (x1),
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.x2 (x2),
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.x3 (x3),
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.x4 (x4),
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.x5 (x5),
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.x6 (x6),
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.x7 (x7),
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.x8 (x8),
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.x9 (x9),
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.z1 (z1),
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.z2 (z2),
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.z3 (z3),
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.z4 (z4),
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.z5 (z5),
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.z6 (z6),
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.z7 (z7),
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// Inputs
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.clk (clk),
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.i (i[31:0]));
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// Aggregate outputs into a single result vector
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// verilator lint_off WIDTH
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wire [63:0] result = {a1,a2,a3,a4,a5,
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o1,o2,o3,o4,o5,
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x1,x2,x3,x4,x5};
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wire [63:0] result = {a1,a2,a3,a4,a5,a6,a7,a8,a9,a10,a11,
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o1,o2,o3,o4,o5,o6,o7,o8,o9,o10,o11,
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x1,x2,x3,x4,x5,x6,x7,x8,x9};
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// verilator lint_on WIDTH
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// Test loop
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always @ (posedge clk) begin
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`ifdef TEST_VERBOSE
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$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
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$display("a %b %b %b %b %b", a1, a2, a3, a4, a5);
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$display("o %b %b %b %b %b", o1, o2, o3, o4, o5);
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$display("x %b %b %b %b %b", x1, x2, x3, x4, x5);
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$display("a %b %b %b %b %b %b %b %b %b %b %b", a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11);
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$display("o %b %b %b %b %b %b %b %b %b %b %b", o1, o2, o3, o4, o5, o6, o7, o8, o9, o10, o11);
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$display("x %b %b %b %b %b %b %b %b %b", x1, x2, x3, x4, x5, x6, x7, x8, x9);
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`endif
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cyc <= cyc + 1;
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crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
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@ -96,23 +136,33 @@ module t(/*AUTOARG*/
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if (a1 != a3) $stop;
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if (a1 != a4) $stop;
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if (a1 != a5) $stop;
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if (a6 != a7) $stop;
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if (a8 != a9) $stop;
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if (o1 != o2) $stop;
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if (o1 != o3) $stop;
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if (o1 != o4) $stop;
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if (o1 != o5) $stop;
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if (o6 != o7) $stop;
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if (o8 != o9) $stop;
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if (x1 != x2) $stop;
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if (x1 != x3) $stop;
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if (x1 != x4) $stop;
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if (x1 != x5) $stop;
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if (x1 != x6) $stop;
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if (x1 != x7) $stop;
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if (z1 != '0) $stop;
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if (z2 != '1) $stop;
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if (z3 != '0) $stop;
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if (z4 != '0) $stop;
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if (z5 != '1) $stop;
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if (z6 != '1) $stop;
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if (z7 != '0) $stop;
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end
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else begin
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$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
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if (crc !== 64'hc77bb9b3784ea091) $stop;
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// What checksum will we end up with (above print should match)
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`define EXPECTED_SUM 64'hd7bd9c247dc7243c
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`define EXPECTED_SUM 64'he9b854d521ebb8b6
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if (sum !== `EXPECTED_SUM) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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@ -123,7 +173,10 @@ endmodule
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module Test(/*AUTOARG*/
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// Outputs
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a1, a2, a3, a4, a5, o1, o2, o3, o4, o5, x1, x2, x3, x4, x5, z1, z2, z3,
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a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11,
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o1, o2, o3, o4, o5, o6, o7, o8, o9, o10, o11,
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x1, x2, x3, x4, x5, x6, x7, x8, x9,
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z1, z2, z3, z4, z5, z6, z7,
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// Inputs
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clk, i
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);
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@ -131,10 +184,13 @@ module Test(/*AUTOARG*/
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input clk;
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input [31:0] i;
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output logic a1, a2, a3, a4, a5;
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output logic o1, o2, o3, o4, o5;
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output logic x1, x2, x3, x4, x5;
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output logic z1, z2, z3;
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output logic a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11;
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output logic o1, o2, o3, o4, o5, o6, o7, o8, o9, o10, o11;
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output logic x1, x2, x3, x4, x5, x6, x7, x8, x9;
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output logic z1, z2, z3, z4, z5, z6, z7;
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logic [127:0] d;
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always_ff @(posedge clk) d <= {i, ~i, ~i, i};
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always_ff @(posedge clk) begin
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a1 <= (i[5] & ~i[3] & i[1]);
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@ -142,23 +198,43 @@ module Test(/*AUTOARG*/
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a3 <= &{i[5], ~i[3], i[1]};
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a4 <= ((i & 32'b101010) == 32'b100010);
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a5 <= ((i & 32'b001010) == 32'b000010) & i[5];
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a6 <= &i[5:3];
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a7 <= i[5] & i[4] & i[3] & i[5] & i[4];
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a8 <= &(~i[5:3]);
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a9 <= ~i[5] & !i[4] & !i[3] && ~i[5] && !i[4];
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a10 <= ~(i[5] & ~d[3]) & (!i[5] & d[1]); // cannot be optimized
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a11 <= d[0] & d[33] & d[66] & d[99] & !d[31] & !d[62] & !d[93] & !d[124];
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//
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o1 <= (~i[5] | i[3] | ~i[1]);
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o2 <= (i[5]!=1 | i[3]!=0 | i[1]!=1);
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o3 <= |{~i[5], i[3], ~i[1]};
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o4 <= ((i & 32'b101010) != 32'b100010);
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o5 <= ((i & 32'b001010) != 32'b000010) | !i[5];
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o6 <= |i[5:3];
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o7 <= i[5] | i[4] | i[3] | i[5] | i[4];
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o8 <= |(~i[5:3]);
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o9 <= ~i[5] | !i[4] | ~i[3] || !i[5] || ~i[4];
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o10 <= ~(~i[5] | d[3]) | (i[5] | ~d[1]); // cannot be optimized
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o11 <= d[0] | d[33] | d[66] | d[99] | !d[31] | !d[62] | !d[93] | !d[124];
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//
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x1 <= (i[5] ^ ~i[3] ^ i[1]);
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x2 <= (i[5]==1 ^ i[3]==0 ^ i[1]==1);
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x3 <= ^{i[5], ~i[3], i[1]};
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x4 <= ^((i & 32'b101010) ^ 32'b001000);
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x5 <= ^((i & 32'b001010) ^ 32'b001000) ^ i[5];
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x6 <= i[5] ^ ~i[3] ^ i[1] ^ i[3] ^ !i[1] ^ i[3] ^ ~i[1];
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x7 <= i[5] ^ (^((i & 32'b001010) ^ 32'b001000));
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x8 <= ~(~i[5] ^ d[3]) ^ (i[5] ^ ~d[1]);
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x9 <= d[0] ^ d[33] ^ d[66] ^ d[99] ^ !d[31] ^ !d[62] ^ !d[93] ^ !d[124];
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//
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// All zero/all one cases
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z1 <= (i[5] & ~i[3] & ~i[5]);
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z2 <= (~i[5] | i[3] | i[5]);
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z3 <= (i[5] ^ ~i[3] ^ ~i[5] ^ i[3]);
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z4 <= &(i[0] && !i[0]);
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z5 <= |(i[1] || !i[1]);
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z6 <= ^(i[2] ^ !i[2]);
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z7 <= ^(i[2] ^ i[2]);
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end
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endmodule
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