From c0499da28b13d2dcf61eca2a2b756dcb0e5e3936 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Fri, 23 Dec 2022 11:32:38 -0500 Subject: [PATCH] Spelling fixes --- bin/verilator | 2 +- include/verilated.h | 2 +- include/verilated_funcs.h | 2 +- include/verilated_save.cpp | 2 +- include/verilated_trace_imp.h | 4 ++-- src/V3Active.cpp | 2 +- src/V3Ast.h | 2 +- src/V3AstNodes.cpp | 2 +- src/V3Const.cpp | 2 +- src/V3Dfg.h | 4 ++-- src/V3DfgDecomposition.cpp | 2 +- src/V3EmitMk.cpp | 2 +- src/V3File.h | 2 +- src/V3Gate.cpp | 2 +- src/V3Global.h | 2 +- src/V3Hasher.cpp | 2 +- src/V3HierBlock.cpp | 2 +- src/V3LinkResolve.cpp | 2 +- src/V3MergeCond.cpp | 2 +- src/V3Options.h | 2 +- src/V3Order.cpp | 2 +- src/V3PairingHeap.h | 2 +- src/V3Param.cpp | 6 +++--- src/V3Partition.cpp | 16 ++++++++-------- src/V3ProtectLib.cpp | 2 +- src/V3SchedPartition.cpp | 4 ++-- src/V3SplitVar.cpp | 6 +++--- src/V3Tristate.cpp | 2 +- src/V3Width.cpp | 2 +- src/Verilator.cpp | 2 +- src/verilog.y | 6 +++--- test_regress/t/t_a5_attributes_include.pl | 2 +- test_regress/t/t_a5_attributes_src.pl | 2 +- test_regress/t/t_dfg_3817.pl | 2 +- test_regress/t/t_dfg_3817.v | 2 +- test_regress/t/t_dotfiles.pl | 2 +- test_regress/t/t_flag_verilate.pl | 4 ++-- test_regress/t/t_hier_block0_bad.out | 2 +- test_regress/t/t_var_sc_bv.cpp | 2 +- 39 files changed, 56 insertions(+), 56 deletions(-) diff --git a/bin/verilator b/bin/verilator index 02506165f..e2ffd163c 100755 --- a/bin/verilator +++ b/bin/verilator @@ -445,7 +445,7 @@ detailed descriptions of these arguments. --unused-regexp Tune UNUSED lint signals -V Verbose version and config -v Verilog library - --no-verilate Skip verilation and just compile previously Verilated code + --no-verilate Skip Verilation and just compile previously Verilated code +verilog1995ext+ Synonym for +1364-1995ext+ +verilog2001ext+ Synonym for +1364-2001ext+ --version Displays program version and exits diff --git a/include/verilated.h b/include/verilated.h index 9186ed69c..315a9f81f 100644 --- a/include/verilated.h +++ b/include/verilated.h @@ -364,7 +364,7 @@ protected: // assumption is that the restore is allowed to pass different arguments struct NonSerializedCommandArgs { // Medium speed - std::vector m_argVec; // Aargument list + std::vector m_argVec; // Argument list bool m_argVecLoaded = false; // Ever loaded argument list } m_args VL_GUARDED_BY(m_argMutex); diff --git a/include/verilated_funcs.h b/include/verilated_funcs.h index 6e938135d..f6bf0ea61 100644 --- a/include/verilated_funcs.h +++ b/include/verilated_funcs.h @@ -506,7 +506,7 @@ static inline void VL_ASSIGNBIT_WO(int bit, WDataOutP owp) VL_MT_SAFE { int32_t lsb = 0; \ uint32_t* chunkp = _butemp.get_raw(); \ while (lsb + VL_SC_BITS_PER_DIGIT < (obits)) { \ - static_assert(std::is_same::value, "IData and EData missmatch"); \ + static_assert(std::is_same::value, "IData and EData mismatch"); \ const uint32_t data = VL_SEL_IWII(lsb + VL_SC_BITS_PER_DIGIT + 1, (rwp).data(), lsb, \ VL_SC_BITS_PER_DIGIT); \ *chunkp = data & VL_MASK_E(VL_SC_BITS_PER_DIGIT); \ diff --git a/include/verilated_save.cpp b/include/verilated_save.cpp index a4dd64562..13e6bf7e4 100644 --- a/include/verilated_save.cpp +++ b/include/verilated_save.cpp @@ -60,7 +60,7 @@ static const char* const VLTSAVE_TRAILER_STR = "vltsaved"; //============================================================================= //============================================================================= //============================================================================= -// Searalization +// Serialization bool VerilatedDeserialize::readDiffers(const void* __restrict datap, size_t size) VL_MT_UNSAFE_ONE { diff --git a/include/verilated_trace_imp.h b/include/verilated_trace_imp.h index 2aba690b5..1c36e8059 100644 --- a/include/verilated_trace_imp.h +++ b/include/verilated_trace_imp.h @@ -497,7 +497,7 @@ void VerilatedTrace::runCallbacks(const std::vectornumThreads() + 1; // Main thread executes all jobs with index % threads == 0 std::vector mainThreadWorkerData; - // Enuque all the jobs + // Enqueue all the jobs for (unsigned i = 0; i < cbVec.size(); ++i) { const CallbackRecord& cbr = cbVec[i]; // Always get the trace buffer on the main thread @@ -793,7 +793,7 @@ static inline void cvtSDataToStr(char* dstp, SData value) { static inline void cvtIDataToStr(char* dstp, IData value) { #ifdef VL_HAVE_AVX2 // Similar to cvtSDataToStr but the bottom 16-bits are processed in the - // top half of the YMM registerss + // top half of the YMM registers const __m256i a = _mm256_insert_epi32(_mm256_undefined_si256(), value, 0); const __m256i b = _mm256_permute4x64_epi64(a, 0); const __m256i s = _mm256_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, diff --git a/src/V3Active.cpp b/src/V3Active.cpp index 6f60a4b21..258218443 100644 --- a/src/V3Active.cpp +++ b/src/V3Active.cpp @@ -86,7 +86,7 @@ protected: } // Recursively traverse the graph to determine whether every control 'BLOCK' has an assignment - // to the output we are currently analysing (the output whose 'user() is set), if so return + // to the output we are currently analyzing (the output whose 'user() is set), if so return // true. Where a BLOCK contains a BRANCH, both the if and else sides of the branch must return // true for the BRANCH to evaluate to true. A BLOCK however needs only a single one of its // siblings to evaluate true in order to evaluate true itself. On output vertex only evaluates diff --git a/src/V3Ast.h b/src/V3Ast.h index e303c989c..d086947b3 100644 --- a/src/V3Ast.h +++ b/src/V3Ast.h @@ -2207,7 +2207,7 @@ AstNode* AstNode::addNext(AstNode* nodep, AstNode* newp); // Inline method implementations AstNode* AstNode::addNext(AstNode* newp) { return addNext(this, newp); } -// Specialisations of privateTypeTest +// Specializations of privateTypeTest #include "V3Ast__gen_type_tests.h" // From ./astgen // Specializations of AstNode::mayBeUnder diff --git a/src/V3AstNodes.cpp b/src/V3AstNodes.cpp index 578131836..4223b3c75 100644 --- a/src/V3AstNodes.cpp +++ b/src/V3AstNodes.cpp @@ -1158,7 +1158,7 @@ static bool sameInit(const AstInitArray* ap, const AstInitArray* bp) { // Compare initializer arrays by value. Note this is only called when they hash the same, // so they likely run at most once per call to 'AstConstPool::findTable'. // This assumes that the defaults are used in the same way. - // TODO when buinding the AstInitArray, remove any values matching the default + // TODO when building the AstInitArray, remove any values matching the default const auto& amapr = ap->map(); const auto& bmapr = bp->map(); const auto ait = amapr.cbegin(); diff --git a/src/V3Const.cpp b/src/V3Const.cpp index 4c2640d7f..b4a7d3f47 100644 --- a/src/V3Const.cpp +++ b/src/V3Const.cpp @@ -2719,7 +2719,7 @@ private: if (nodep->isClocked()) { // A constant can never get a pos/negedge if (onlySenItemInSenTree(nodep)) { if (nodep->edgeType() == VEdgeType::ET_CHANGED) { - // TODO: This really is dodgy, as strictgly compliant simulators will not + // TODO: This really is dodgy, as strictly compliant simulators will not // execute this block, but but t_func_check relies on it nodep->replaceWith( new AstSenItem{nodep->fileline(), AstSenItem::Initial{}}); diff --git a/src/V3Dfg.h b/src/V3Dfg.h index 5d86805f8..7dd5a5c69 100644 --- a/src/V3Dfg.h +++ b/src/V3Dfg.h @@ -125,7 +125,7 @@ class DfgGraph final { // Variables and constants make up a significant proportion of vertices (40-50% was observed // in large designs), and they can often be treated specially in algorithms, which in turn - // enables significant verilation performance gains, so we keep these in separate lists for + // enables significant Verilation performance gains, so we keep these in separate lists for // direct access. V3List m_varVertices; // The variable vertices in the graph V3List m_constVertices; // The constant vertices in the graph @@ -559,7 +559,7 @@ public: virtual const string srcName(size_t idx) const = 0; }; -// Specialisations of privateTypeTest +// Specializations of privateTypeTest #include "V3Dfg__gen_type_tests.h" // From ./astgen //------------------------------------------------------------------------------ diff --git a/src/V3DfgDecomposition.cpp b/src/V3DfgDecomposition.cpp index b81edf12f..58ab733f1 100644 --- a/src/V3DfgDecomposition.cpp +++ b/src/V3DfgDecomposition.cpp @@ -291,7 +291,7 @@ class ExtractCyclicComponents final { // Assign vertex to the target component vtxState.component = targetComponent; - // Visit all neighbours. We stop at variable boundaries, + // Visit all neighbors. We stop at variable boundaries, // which is where we will split the graphs vtx.forEachSource([=](DfgVertex& other) { if (other.is()) return; diff --git a/src/V3EmitMk.cpp b/src/V3EmitMk.cpp index 2964f0bc3..ffbd1e2ae 100644 --- a/src/V3EmitMk.cpp +++ b/src/V3EmitMk.cpp @@ -317,7 +317,7 @@ class EmitMkHierVerilation final { void emit(V3OutMkFile& of) const { of.puts("# Hierarchical Verilation -*- Makefile -*-\n"); of.puts("# DESCR" - "IPTION: Verilator output: Makefile for hierarchical verilatrion\n"); + "IPTION: Verilator output: Makefile for hierarchical Verilation\n"); of.puts("#\n"); of.puts("# The main makefile " + v3Global.opt.prefix() + ".mk calls this makefile\n"); of.puts("\n"); diff --git a/src/V3File.h b/src/V3File.h index ba2b5c6d1..f44638614 100644 --- a/src/V3File.h +++ b/src/V3File.h @@ -126,7 +126,7 @@ private: bool m_inStringLiteral = false; int m_indentLevel = 0; // Current {} indentation std::stack m_parenVec; // Stack of columns where last ( was - int m_bracketLevel = 0; // Intenting = { block, indicates number of {'s seen. + int m_bracketLevel = 0; // Indenting = { block, indicates number of {'s seen. int endLevels(const char* strg); void putcNoTracking(char chr); diff --git a/src/V3Gate.cpp b/src/V3Gate.cpp index 0f82d8730..e032d1ca1 100644 --- a/src/V3Gate.cpp +++ b/src/V3Gate.cpp @@ -593,7 +593,7 @@ void GateVisitor::optimizeSignals(bool allowMultiIn) { if (!logicVertexp->reducible()) continue; AstNode* const logicp = logicVertexp->nodep(); - // Commit pendingg optimizations to driving logic, as we will re-analyse + // Commit pending optimizations to driving logic, as we will re-analyze commitElimVar(logicp); // Can we eliminate? diff --git a/src/V3Global.h b/src/V3Global.h index 7807d6f2b..16b6fd851 100644 --- a/src/V3Global.h +++ b/src/V3Global.h @@ -93,7 +93,7 @@ class V3Global final { // Globals AstNetlist* m_rootp = nullptr; // Root of entire netlist, // created by makeInitNetlist(} so static constructors run first - V3HierBlockPlan* m_hierPlanp = nullptr; // Hierarchical verilation plan, + V3HierBlockPlan* m_hierPlanp = nullptr; // Hierarchical Verilation plan, // nullptr unless hier_block, set via hierPlanp(V3HierBlockPlan*} VWidthMinUsage m_widthMinUsage = VWidthMinUsage::LINT_WIDTH; // What AstNode::widthMin() is used for diff --git a/src/V3Hasher.cpp b/src/V3Hasher.cpp index 2b72c0bc5..cd97307bc 100644 --- a/src/V3Hasher.cpp +++ b/src/V3Hasher.cpp @@ -300,7 +300,7 @@ private: } //------------------------------------------------------------ - // AstNode direct descendents + // AstNode direct descendants void visit(AstNodeRange* nodep) override { m_hash += hashNodeAndIterate(nodep, HASH_DTYPE, HASH_CHILDREN, [=]() {}); } diff --git a/src/V3HierBlock.cpp b/src/V3HierBlock.cpp index e1f258ccd..8bc116864 100644 --- a/src/V3HierBlock.cpp +++ b/src/V3HierBlock.cpp @@ -1,6 +1,6 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* -// DESCRIPTION: Verilator: Hierarchical verilation for large designs +// DESCRIPTION: Verilator: Hierarchical Verilation for large designs // // Code available from: https://verilator.org // diff --git a/src/V3LinkResolve.cpp b/src/V3LinkResolve.cpp index 06d1bc27e..953ca7a2b 100644 --- a/src/V3LinkResolve.cpp +++ b/src/V3LinkResolve.cpp @@ -59,7 +59,7 @@ private: // VISITs // TODO: Most of these visitors are here for historical reasons. - // TODO: ExpectDecriptor can move to data type resolution, and the rest + // TODO: ExpectDescriptor can move to data type resolution, and the rest // TODO: could move to V3LinkParse to get them out of the way of elaboration void visit(AstNodeModule* nodep) override { // Module: Create sim table for entire module and iterate diff --git a/src/V3MergeCond.cpp b/src/V3MergeCond.cpp index 51f4e1679..9397e7f26 100644 --- a/src/V3MergeCond.cpp +++ b/src/V3MergeCond.cpp @@ -138,7 +138,7 @@ bool areDisjoint(const std::set& a, const std::set struct StmtProperties { AstNodeExpr* m_condp = nullptr; // The condition expression, if a conditional node std::set m_rdVars; // Variables read by this statement - std::set m_wrVars; // Variables writen by this statement + std::set m_wrVars; // Variables written by this statement bool m_isFence = false; // Nothing should move across this statement, nor should it be merged AstNodeStmt* m_prevWithSameCondp = nullptr; // Previous node in same list, with same condition bool writesConditionVar() const { diff --git a/src/V3Options.h b/src/V3Options.h index 1665c6167..87dd60b6a 100644 --- a/src/V3Options.h +++ b/src/V3Options.h @@ -638,7 +638,7 @@ public: bool hierTop() const VL_MT_SAFE { return !m_hierChild && !m_hierBlocks.empty(); } const V3HierBlockOptSet& hierBlocks() const { return m_hierBlocks; } // Directory to save .tree, .dot, .dat, .vpp for hierarchical block top - // Returns makeDir() unless top module of hierarchical verilation. + // Returns makeDir() unless top module of hierarchical Verilation. string hierTopDataDir() const VL_MT_SAFE { return hierTop() ? (makeDir() + '/' + prefix() + "__hier.dir") : makeDir(); } diff --git a/src/V3Order.cpp b/src/V3Order.cpp index 1d0c0ac53..4b58f254a 100644 --- a/src/V3Order.cpp +++ b/src/V3Order.cpp @@ -217,7 +217,7 @@ class OrderBuildVisitor final : public VNVisitor { m_inClocked = senTreep->hasClocked(); - // Note: We don't need to analyse the sensitivity list, as currently all sensitivity + // Note: We don't need to analyze the sensitivity list, as currently all sensitivity // lists simply reference an entry in a trigger vector, which are all set external to // the code being ordered. diff --git a/src/V3PairingHeap.h b/src/V3PairingHeap.h index d7dc489d4..6d824a298 100644 --- a/src/V3PairingHeap.h +++ b/src/V3PairingHeap.h @@ -27,7 +27,7 @@ // // While this is written as a generic data structure, it's interface and // implementation is finely tuned for it's use by V3Parm_tition, and is critical -// to verilaton performance, so be very careful changing anything or adding any +// to Verilation performance, so be very careful changing anything or adding any // new operations that would impact either memory usage, or performance of the // existing operations. This data structure is fully deterministic, meaning // the order in which elements with equal keys are retrieved only depends on diff --git a/src/V3Param.cpp b/src/V3Param.cpp index 421586b3e..75ebb3409 100644 --- a/src/V3Param.cpp +++ b/src/V3Param.cpp @@ -79,7 +79,7 @@ class ParameterizedHierBlocks final { // MEMBERS // key:Original module name, value:HiearchyBlockOption* - // If a module is parameterized, the module is uniquiefied to overridden parameters. + // If a module is parameterized, the module is uniquified to overridden parameters. // This is why HierBlockOptsByOrigName is multimap. HierBlockOptsByOrigName m_hierBlockOptsByOrigName; // key:mangled module name, value:AstNodeModule* @@ -442,7 +442,7 @@ class ParamProcessor final { } } } - // Check if parameter setting during instantiation is simple enough for hierarchical verilation + // Check if parameter setting during instantiation is simple enough for hierarchical Verilation void checkSupportedParam(AstNodeModule* modp, AstPin* pinp) const { // InitArray and AstParamTypeDType are not supported because that can not be set via -G // option. @@ -453,7 +453,7 @@ class ParamProcessor final { } if (!supported) { pinp->v3error(AstNode::prettyNameQ(modp->origName()) - << " has hier_block metacomment, hierarchical verilation" + << " has hier_block metacomment, hierarchical Verilation" << " supports only integer/floating point/string parameters"); } } else { diff --git a/src/V3Partition.cpp b/src/V3Partition.cpp index 07223f2fd..e147372c7 100644 --- a/src/V3Partition.cpp +++ b/src/V3Partition.cpp @@ -1119,7 +1119,7 @@ public: // of a rescore, in case its score has fallen and we need to move it up // toward the front of the scoreboard. // -// Wait, whaaat? Shouldn't the scores only increase as we merge nodes? Well +// Wait, what? Shouldn't the scores only increase as we merge nodes? Well // that's almost true. But there is one exception. // // Suppose we have A->B, B->C, and A->C. @@ -1652,12 +1652,12 @@ private: // Need at least 2 edges if (!mtaskp->beginp(way) || !mtaskp->beginp(way)->nextp(way)) return; - std::array neighbours; + std::array neighbors; // This is a hot method, so we want so sort as efficiently as possible. We pre-load // all data (critical path cost and id) required for determining ordering into an aligned // structure. There is not enough space next to these to keep a whole pointer within 16 - // bytes, so we store an index into the neighbours buffer instead. We can then compare + // bytes, so we store an index into the neighbors buffer instead. We can then compare // and swap these sorting records very efficiently. With this the standard library sorting // functions are efficient enough and using more optimized methods (e.g.: sorting networks) // has no measurable benefit. @@ -1666,7 +1666,7 @@ private: uint32_t m_cp; uint8_t m_idx; static_assert(PART_SIBLING_EDGE_LIMIT <= std::numeric_limits::max(), - "m_idx must fit all indices into 'neighbours'"); + "m_idx must fit all indices into 'neighbors'"); bool operator<(const SortingRecord& that) const { return m_cp < that.m_cp || (m_cp == that.m_cp && m_id < that.m_id); } @@ -1680,7 +1680,7 @@ private: for (V3GraphEdge *edgep = mtaskp->beginp(way), *nextp; edgep; edgep = nextp) { nextp = edgep->nextp(way); // Fetch next first as likely cache miss LogicMTask* const otherp = static_cast(edgep->furtherp(way)); - neighbours[n] = otherp; + neighbors[n] = otherp; sortRecs[n].m_id = otherp->id(); sortRecs[n].m_cp = otherp->critPathCost(way) + otherp->cost(); sortRecs[n].m_idx = n; @@ -1697,13 +1697,13 @@ private: const size_t end = n & ~static_cast(1); // Round down to even, (we want pairs) std::sort(sortRecs.begin(), sortRecs.begin() + n); for (size_t i = 0; i < end; i += 2) { - makeSiblingMC(neighbours[sortRecs[i].m_idx], neighbours[sortRecs[i + 1].m_idx]); + makeSiblingMC(neighbors[sortRecs[i].m_idx], neighbors[sortRecs[i + 1].m_idx]); } } else { constexpr size_t end = 2 * MAX_NONEXHAUSTIVE_PAIRS; std::partial_sort(sortRecs.begin(), sortRecs.begin() + end, sortRecs.begin() + n); for (size_t i = 0; i < end; i += 2) { - makeSiblingMC(neighbours[sortRecs[i].m_idx], neighbours[sortRecs[i + 1].m_idx]); + makeSiblingMC(neighbors[sortRecs[i].m_idx], neighbors[sortRecs[i + 1].m_idx]); } } } @@ -1907,7 +1907,7 @@ private: // // ABOUT UNORDERED WRITE-READ PAIRS // -// If we don't put unordered write-read pairs into some order at verilation +// If we don't put unordered write-read pairs into some order at Verilation // time, we risk a runtime race. // // How do such unordered writer/reader pairs happen? Here's a partial list diff --git a/src/V3ProtectLib.cpp b/src/V3ProtectLib.cpp index 27a088878..85cbe2647 100644 --- a/src/V3ProtectLib.cpp +++ b/src/V3ProtectLib.cpp @@ -151,7 +151,7 @@ private: // Timescale if (v3Global.opt.hierChild() && v3Global.rootp()->timescaleSpecified()) { - // Emit timescale for hierarchical verilation if input HDL specifies timespec + // Emit timescale for hierarchical Verilation if input HDL specifies timespec txtp->addText(fl, std::string{"timeunit "} + modp->timeunit().ascii() + ";\n"); txtp->addText(fl, std::string{"timeprecision "} + +v3Global.rootp()->timeprecision().ascii() + ";\n"); diff --git a/src/V3SchedPartition.cpp b/src/V3SchedPartition.cpp index b356afde1..05d44b7ad 100644 --- a/src/V3SchedPartition.cpp +++ b/src/V3SchedPartition.cpp @@ -258,7 +258,7 @@ class SchedGraphBuilder final : public VNVisitor { // Default - Any other AstActive content not handled above will hit this void visit(AstNode* nodep) override { // - nodep->v3fatalSrc("Should behandled above"); + nodep->v3fatalSrc("Should be handled above"); } // LCOV_EXCL_STOP @@ -361,7 +361,7 @@ LogicRegions partition(LogicByScope& clockedLogic, LogicByScope& combinationalLo // Partition the Pre logic { const VNUser1InUse user1InUse; // AstVarScope::user1() -> bool: read in Active region - const VNUser2InUse user2InUse; // AstVarScope::user2() -> bool: writen in Active region + const VNUser2InUse user2InUse; // AstVarScope::user2() -> bool: written in Active region const auto markVars = [](AstNode* nodep) { nodep->foreach([](const AstNodeVarRef* vrefp) { diff --git a/src/V3SplitVar.cpp b/src/V3SplitVar.cpp index da1b95c87..f0ea8b6fd 100644 --- a/src/V3SplitVar.cpp +++ b/src/V3SplitVar.cpp @@ -27,7 +27,7 @@ // What this pass does looks as below. // // // Original -// logic [1:0] unpcked_array_var[0:1] /*verilator split_var*/; +// logic [1:0] unpacked_array_var[0:1] /*verilator split_var*/; // always_comb begin // unpacked_array_var[1][0] = unpacked_array_var[0][0]; // UNOPTFLAT warning // unpacked_array_var[1][1] = ~unpacked_array_var[0][1]; // UNOPTFLAT warning @@ -45,8 +45,8 @@ // is initially converted to // // // Intermediate -// logic [1:0] unpcked_array_var0 /*verilator split_var*/; -// logic [1:0] unpcked_array_var1 /*verilator split_var*/; +// logic [1:0] unpacked_array_var0 /*verilator split_var*/; +// logic [1:0] unpacked_array_var1 /*verilator split_var*/; // always_comb begin // unpacked_array_var1[0] = unpacked_array_var0[0]; // unpacked_array_var1[1] = ~unpacked_array_var0[1]; diff --git a/src/V3Tristate.cpp b/src/V3Tristate.cpp index 24cbb7da5..40f80d270 100644 --- a/src/V3Tristate.cpp +++ b/src/V3Tristate.cpp @@ -65,7 +65,7 @@ // // It is possible to statically resolve all drivers when the strongest assignment has RHS marked as // non-tristate. If the RHS is equal to z, that assignment has to be skipped. Since the value may -// be not known at verilation time, cases with tristates on RHS can't be handled statically. +// be not known at Verilation time, cases with tristates on RHS can't be handled statically. // // Static resolution is split into 2 parts. // First part can be done before tristate propagation. It is about removing assignments that are diff --git a/src/V3Width.cpp b/src/V3Width.cpp index 94aca3878..96f8d7af3 100644 --- a/src/V3Width.cpp +++ b/src/V3Width.cpp @@ -7207,7 +7207,7 @@ AstNode* V3Width::widthParamsEdit(AstNode* nodep) { //! later to do the width check. //! @return Pointer to the edited node. AstNode* V3Width::widthGenerateParamsEdit( - AstNode* nodep) { //!< [in] AST whose parameters widths are to be analysed. + AstNode* nodep) { //!< [in] AST whose parameters widths are to be analyzed. UINFO(4, __FUNCTION__ << ": " << nodep << endl); // We should do it in bottom-up module order, but it works in any order. WidthVisitor visitor{true, true}; diff --git a/src/Verilator.cpp b/src/Verilator.cpp index aad4863cd..026169109 100644 --- a/src/Verilator.cpp +++ b/src/Verilator.cpp @@ -159,7 +159,7 @@ static void process() { V3Dead::deadifyModules(v3Global.rootp()); v3Global.checkTree(); - // Create a hierarchical verilation plan + // Create a hierarchical Verilation plan if (!v3Global.opt.lintOnly() && !v3Global.opt.xmlOnly() && v3Global.opt.hierarchical()) { V3HierBlockPlan::createPlan(v3Global.rootp()); // If a plan is created, further analysis is not necessary. diff --git a/src/verilog.y b/src/verilog.y index 114e3da12..06f47da7e 100644 --- a/src/verilog.y +++ b/src/verilog.y @@ -1560,7 +1560,7 @@ portSig: // Interface headers interface_declaration: // IEEE: interface_declaration + interface_nonansi_header + interface_ansi_header: - // // timeunits_delcarationE is instead in interface_item + // // timeunits_declarationE is instead in interface_item intFront importsAndParametersE portsStarE ';' interface_itemListE yENDINTERFACE endLabelE { if ($2) $1->addStmtsp($2); @@ -1648,7 +1648,7 @@ anonymous_program_item: // ==IEEE: anonymous_program_item ; program_declaration: // IEEE: program_declaration + program_nonansi_header + program_ansi_header: - // // timeunits_delcarationE is instead in program_item + // // timeunits_declarationE is instead in program_item pgmFront parameter_port_listE portsStarE ';' /*cont*/ program_itemListE yENDPROGRAM endLabelE { $1->modTrace(GRAMMARP->allTracingOn($1->fileline())); // Stash for implicit wires, etc @@ -4029,7 +4029,7 @@ system_f_call: // IEEE: system_tf_call (as func) | system_f_call_or_t { $$ = $1; } ; -systemDpiArgsE: // IEEE: part of system_if_call for aruments of $dpi call +systemDpiArgsE: // IEEE: part of system_if_call for arguments of $dpi call parenE { $$ = nullptr; } | '(' exprList ')' { $$ = GRAMMARP->argWrapList($2); } ; diff --git a/test_regress/t/t_a5_attributes_include.pl b/test_regress/t/t_a5_attributes_include.pl index e0eb8915e..6c69c95e3 100755 --- a/test_regress/t/t_a5_attributes_include.pl +++ b/test_regress/t/t_a5_attributes_include.pl @@ -17,7 +17,7 @@ if ($ENV{VERILATOR_TEST_NO_ATTRIBUTES}) { } sub check { my $root = ".."; - # some of the files are only used in verilation + # some of the files are only used in Verilation # and are only in "include" folder my @srcfiles = glob("$root/include/*.cpp"); my $srcfiles_str = join(" ", @srcfiles); diff --git a/test_regress/t/t_a5_attributes_src.pl b/test_regress/t/t_a5_attributes_src.pl index ef39a8ed7..8c2447820 100755 --- a/test_regress/t/t_a5_attributes_src.pl +++ b/test_regress/t/t_a5_attributes_src.pl @@ -17,7 +17,7 @@ if ($ENV{VERILATOR_TEST_NO_ATTRIBUTES}) { } sub check { my $root = ".."; - # some of the files are only used in verilation + # some of the files are only used in Verilation # and are only in "include" folder my @srcfiles = grep { !/\/(V3Const|Vlc\w*|\w*_test|\w*_sc|\w*.yy).cpp$/ } glob("$root/src/*.cpp $root/src/obj_opt/V3Const__gen.cpp"); diff --git a/test_regress/t/t_dfg_3817.pl b/test_regress/t/t_dfg_3817.pl index d7e843ed6..4e8f5dbef 100755 --- a/test_regress/t/t_dfg_3817.pl +++ b/test_regress/t/t_dfg_3817.pl @@ -10,7 +10,7 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di scenarios(vlt => 1); -# test case was causing use-after-free and segfaulting during verilation +# test case was causing use-after-free and segfaulting during Verilation compile(); ok(1); diff --git a/test_regress/t/t_dfg_3817.v b/test_regress/t/t_dfg_3817.v index cc2bc2ee2..043142ab7 100644 --- a/test_regress/t/t_dfg_3817.v +++ b/test_regress/t/t_dfg_3817.v @@ -1,5 +1,5 @@ // DESCRIPTION: Verilator: Verilog Test module for issue #3817 -// addDriver() was causing use-after-free and segfaulting during verilation +// addDriver() was causing use-after-free and segfaulting during Verilation // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Jevin Sweval. diff --git a/test_regress/t/t_dotfiles.pl b/test_regress/t/t_dotfiles.pl index 9df77e2ca..c60055256 100755 --- a/test_regress/t/t_dotfiles.pl +++ b/test_regress/t/t_dotfiles.pl @@ -23,7 +23,7 @@ foreach my $dotname ("linkcells", "task_call", "gate_simp", "gate_opt", "ordermv_initial", "ordermv_hazards", "ordermv_contraction", "ordermv_transitive1", "orderg_done", "ordermv_transitive2", "schedule") { # Some files with identical prefix are generated multiple times during - # verilation. Ensure that at least one of each $dotname-prefixed file is generated. + # Verilation. Ensure that at least one of each $dotname-prefixed file is generated. @dotFiles = glob("$Self->{obj_dir}/*$dotname.dot"); if (scalar @dotFiles == 0) { error("Found no dotfiles with pattern *$dotname.dot"); diff --git a/test_regress/t/t_flag_verilate.pl b/test_regress/t/t_flag_verilate.pl index 649eac752..bf4061315 100755 --- a/test_regress/t/t_flag_verilate.pl +++ b/test_regress/t/t_flag_verilate.pl @@ -23,7 +23,7 @@ compile( # Don't call cmake nor gmake from driver.pl. Nothing should be done he '../' . $Self->{main_filename}] ); -# --no-verilate should skip verilation +# --no-verilate should skip Verilation if ( -e $Self->{obj_dir} . '/Vt_flag_verilate.mk' ) { $Self->error('Vt_flag_verilate.mk is unexpectedly created'); } @@ -41,7 +41,7 @@ if ( ! -e $Self->{obj_dir} . '/Vt_flag_verilate.mk' ) { $Self->error('Vt_flag_verilate.mk does not exist'); } -# Just build, no verilation. .tree must not be saved even with --dump-tree option. +# Just build, no Verilation. .tree must not be saved even with --dump-tree option. compile( # Don't call cmake nor gmake from driver.pl. Just build here verilator_make_cmake => 0, verilator_make_gmake => 0, diff --git a/test_regress/t/t_hier_block0_bad.out b/test_regress/t/t_hier_block0_bad.out index 6f145312f..61e172e54 100644 --- a/test_regress/t/t_hier_block0_bad.out +++ b/test_regress/t/t_hier_block0_bad.out @@ -1,4 +1,4 @@ -%Error: t/t_hier_block0_bad.v:20:11: 'sub0' has hier_block metacomment, hierarchical verilation supports only integer/floating point/string parameters +%Error: t/t_hier_block0_bad.v:20:11: 'sub0' has hier_block metacomment, hierarchical Verilation supports only integer/floating point/string parameters : ... In instance t 20 | sub0 #(UNPACKED) i_sub0(.clk(clk), .in(8'(count)), .out(out0)); | ^~~~~~~~ diff --git a/test_regress/t/t_var_sc_bv.cpp b/test_regress/t/t_var_sc_bv.cpp index d8324bf2f..24e4ab7d7 100644 --- a/test_regress/t/t_var_sc_bv.cpp +++ b/test_regress/t/t_var_sc_bv.cpp @@ -14,7 +14,7 @@ double sc_time_stamp() { return 0; } void compare_signals(const sc_signal>& ls, const sc_signal>& rs) { if (ls.read() != rs.read()) { pass &= false; - VL_PRINTF("%%Error: Data missmatch in signals %s and %s\n", ls.name(), rs.name()); + VL_PRINTF("%%Error: Data mismatch in signals %s and %s\n", ls.name(), rs.name()); } }