From bf2b4e1b6ad45ee0d7fc909c07beab7d00ba6e45 Mon Sep 17 00:00:00 2001
From: Han Qi <my@rhanqtl.com>
Date: Fri, 4 Oct 2024 04:19:07 +0800
Subject: [PATCH] Fix equivalence checking when replacing type parameters
 (#5213) (#5255)

---
 docs/CONTRIBUTORS                       |  1 +
 src/V3Param.cpp                         |  3 ++-
 test_regress/t/t_class_param_rewrite.py | 18 ++++++++++++++++++
 test_regress/t/t_class_param_rewrite.v  | 25 +++++++++++++++++++++++++
 4 files changed, 46 insertions(+), 1 deletion(-)
 create mode 100755 test_regress/t/t_class_param_rewrite.py
 create mode 100644 test_regress/t/t_class_param_rewrite.v

diff --git a/docs/CONTRIBUTORS b/docs/CONTRIBUTORS
index e1bb69c5a..676b8c946 100644
--- a/docs/CONTRIBUTORS
+++ b/docs/CONTRIBUTORS
@@ -65,6 +65,7 @@ Graham Rushton
 Guokai Chen
 Gus Smith
 Gustav Svensk
+Han Qi
 Harald Heckmann
 Hennadii Chernyshchyk
 Howard Su
diff --git a/src/V3Param.cpp b/src/V3Param.cpp
index e29a10f63..fe580f853 100644
--- a/src/V3Param.cpp
+++ b/src/V3Param.cpp
@@ -768,7 +768,8 @@ class ParamProcessor final {
                 }
             }
         } else if (AstParamTypeDType* const modvarp = pinp->modPTypep()) {
-            AstNodeDType* const exprp = VN_CAST(pinp->exprp(), NodeDType);
+            AstNodeDType* rawTypep = VN_CAST(pinp->exprp(), NodeDType);
+            AstNodeDType* const exprp = rawTypep ? rawTypep->skipRefToEnump() : nullptr;
             const AstNodeDType* const origp = modvarp->skipRefToEnump();
             if (!exprp) {
                 pinp->v3error("Parameter type pin value isn't a type: Param "
diff --git a/test_regress/t/t_class_param_rewrite.py b/test_regress/t/t_class_param_rewrite.py
new file mode 100755
index 000000000..d4f986441
--- /dev/null
+++ b/test_regress/t/t_class_param_rewrite.py
@@ -0,0 +1,18 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+
+test.compile()
+
+test.execute()
+
+test.passes()
diff --git a/test_regress/t/t_class_param_rewrite.v b/test_regress/t/t_class_param_rewrite.v
new file mode 100644
index 000000000..17664ec71
--- /dev/null
+++ b/test_regress/t/t_class_param_rewrite.v
@@ -0,0 +1,25 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2024 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+module test;
+  typedef enum { FOO_0 } foo_e;
+  typedef enum { BAR_0 } bar_e;
+
+  class baz #(parameter type E = foo_e);
+    static function void print();
+      E enum_item;
+      if (enum_item.first().name() != "BAR_0")
+        $stop;
+    endfunction
+  endclass
+
+  initial begin
+    baz#(bar_e)::print();
+
+    $write("*-* All Finished *-*\n");
+    $finish;
+  end
+endmodule