Add t_clk_2in test

test_regress/t/t_clk_2in.cpp

@@ -0,0 +1,53 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2010 by Wilson Snyder.
+
+#include <verilated.h>
+#ifdef T_CLK_2IN_VEC
+# include "Vt_clk_2in_vec.h"
+#else
+# include "Vt_clk_2in.h"
+#endif
+
+unsigned int main_time = false;
+
+double sc_time_stamp () {
+    return main_time;
+}
+
+VM_PREFIX* topp = NULL;
+
+void clockit(int clk1, int clk0) {
+#ifdef T_CLK_2IN_VEC
+    topp->clks = clk1<<1 | clk0;
+#else
+    topp->c1 = clk1;
+    topp->c0 = clk0;
+#endif
+#ifdef TEST_VERBOSE
+    printf("[%d] c1=%d c0=%d\n", main_time, clk1, clk0);
+#endif
+    topp->eval();
+    main_time++;
+}
+
+int main (int argc, char *argv[]) {
+    topp = new VM_PREFIX;
+    topp->check = 0;
+    clockit(0,0);
+
+    Verilated::debug(0);
+
+    for (int i = 0; i < 2; i++) {
+	clockit(0, 0);
+	clockit(0, 1);
+	clockit(1, 1);
+	clockit(0, 0);
+	clockit(1, 1);
+	clockit(1, 0);
+	clockit(0, 0);
+    }
+    topp->check = 1;
+    clockit(0,0);
+}

test_regress/t/t_clk_2in.pl

@@ -0,0 +1,20 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+compile (
+	 make_top_shell => 0,
+	 make_main => 0,
+	 v_flags2 => ["--exe $Self->{t_dir}/$Self->{name}.cpp"],
+	 ) if $Self->{v3};
+
+execute (
+	 check_finished=>1,
+	 ) if $Self->{v3};
+ok(1);
+1;

test_regress/t/t_clk_2in.v

@@ -0,0 +1,70 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2010 by Wilson Snyder.
+
+module t (
+`ifdef T_CLK_2IN_VEC
+	  input [1:0] clks,
+`else
+	  input       c0,
+	  input       c1,
+`endif
+	  input check
+   );
+
+`ifdef T_CLK_2IN_VEC
+   wire    c0 = clks[0];
+   wire    c1 = clks[1];
+`endif
+
+   integer p0 = 0;
+   integer p1 = 0;
+   integer p01 = 0;
+   integer n0 = 0;
+   integer n1 = 0;
+   integer n01 = 0;
+
+`define display_counts(text) begin \
+   $write("[%0t] ",$time); \
+   `ifdef T_CLK_2IN_VEC $write(" 2v "); `endif \
+   $write(text); \
+   $write(": %0d %0d %0d %0d %0d %0d\n",  p0, p1, p01, n0, n1, n01); \
+   end
+
+   always @ (posedge c0) begin
+      p0 = p0 + 1;  // Want blocking, so don't miss clock counts
+`ifdef TEST_VERBOSE `display_counts("posedge 0"); `endif
+   end
+   always @ (posedge c1) begin
+      p1 = p1 + 1;
+`ifdef TEST_VERBOSE `display_counts("posedge 1"); `endif
+   end
+   always @ (posedge c0 or posedge c1) begin
+      p01 = p01 + 1;
+`ifdef TEST_VERBOSE `display_counts("posedge *"); `endif
+   end
+   always @ (negedge c0) begin
+      n0 = n0 + 1;
+`ifdef TEST_VERBOSE `display_counts("negedge 0"); `endif
+   end
+   always @ (negedge c1) begin
+      n1 = n1 + 1;
+`ifdef TEST_VERBOSE `display_counts("negedge 1"); `endif
+   end
+   always @ (negedge c0 or negedge c1) begin
+      n01 = n01 + 1;
+`ifdef TEST_VERBOSE `display_counts("negedge *"); `endif
+   end
+
+   always @ (posedge check) begin
+      if (p0!=4) $stop;
+      if (p1!=4) $stop;
+      if (p01!=6) $stop;
+      if (n0!=4) $stop;
+      if (n1!=4) $stop;
+      if (n01!=6) $stop;
+      $write("*-* All Finished *-*\n");
+   end
+
+endmodule

test_regress/t/t_clk_2in_vec.pl

@@ -0,0 +1,22 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+top_filename("t/t_clk_2in.v");
+
+compile (
+	 make_top_shell => 0,
+	 make_main => 0,
+	 v_flags2 => ["+define+T_CLK_2IN_VEC=1 --exe $Self->{t_dir}/t_clk_2in.cpp"],
+	 ) if $Self->{v3};
+
+execute (
+	 check_finished=>1,
+	 ) if $Self->{v3};
+ok(1);
+1;