From be8f1a25c6d57fcb3cfc26fb012eacc6d9e421c5 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Mon, 24 Aug 2020 08:58:33 -0400 Subject: [PATCH] Commentary (#2510) --- bin/verilator | 30 +++++++++++++++++++----------- 1 file changed, 19 insertions(+), 11 deletions(-) diff --git a/bin/verilator b/bin/verilator index 1a1354666..db91edb88 100755 --- a/bin/verilator +++ b/bin/verilator @@ -4199,17 +4199,7 @@ default as a code style warning. =item BLKANDNBLK BLKANDNBLK is an error that a variable comes from a mix of blocking and -non-blocking assignments. Generally, this is caused by a register driven -by both combo logic and a flop: - - always @ (posedge clk) foo[0] <= ... - always @* foo[1] = ... - -Simply use a different register for the flop: - - always @ (posedge clk) foo_flopped[0] <= ... - always @* foo[0] = foo_flopped[0]; - always @* foo[1] = ... +non-blocking assignments. This is not illegal in SystemVerilog, but a violation of good coding practice. Verilator reports this as an error, because ignoring this warning @@ -4220,6 +4210,24 @@ BLKANDNBLK" metacomment or the -Wno-BLKANDNBLK option) when one of the assignments is inside a public task, or when the blocking and non-blocking assignments have non-overlapping bits and structure members. +Generally, this is caused by a register driven by both combo logic and a +flop: + + logic [1:0] foo; + always @ (posedge clk) foo[0] <= ... + always @* foo[1] = ... + +Simply use a different register for the flop: + + logic [1:0] foo; + always @ (posedge clk) foo_flopped[0] <= ... + always @* foo[0] = foo_flopped[0]; + always @* foo[1] = ... + +Or, this may also avoid the error: + + logic [1:0] foo /*verilator split_var*/; + =item BLKSEQ This indicates that a blocking assignment (=) is used in a sequential