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Match Verilog-Perl: Fix parse error on min:typ:max delay pairs

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git-svn-id: file://localhost/svn/verilator/trunk/verilator@1018 77ca24e4-aefa-0310-84f0-b9a241c72d87
This commit is contained in:
Wilson Snyder 2008-03-31 21:03:56 +00:00
parent 61fbab1910
commit bd60cf12f8
2 changed files with 8 additions and 6 deletions
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2
src/V3PreProc.cpp
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@ -562,7 +562,7 @@ int V3PreProcImp::getRawToken() {
if (m_lineAdd) {
m_lineAdd--;
m_rawAtBol = true;
yytext="\n"; yyleng=1;
yytext=(char*)"\n"; yyleng=1;
return (VP_TEXT);
}
if (m_lineCmt!="") {

12
src/verilog.y
View File

@ -382,7 +382,7 @@ class AstSenTree;
%type<nodep> modItem modItemList modItemListE modOrGenItem
%type<nodep> generateRegion
%type<nodep> genItem genItemList genItemBegin genItemBlock genTopBlock genCaseListE genCaseList
%type<nodep> dlyTerm
%type<nodep> dlyTerm minTypMax
%type<fileline> delay
%type<varp> sigAndAttr sigId sigIdRange sigList regsig regsigList regSigId
%type<varp> netSig netSigList
@ -696,9 +696,9 @@ delayE: /* empty */ { }
;
delay: '#' dlyTerm { $$ = $1; } /* ignored */
| '#' '(' dlyInParen ')' { $$ = $1; } /* ignored */
| '#' '(' dlyInParen ',' dlyInParen ')' { $$ = $1; } /* ignored */
| '#' '(' dlyInParen ',' dlyInParen ',' dlyInParen ')' { $$ = $1; } /* ignored */
| '#' '(' minTypMax ')' { $$ = $1; } /* ignored */
| '#' '(' minTypMax ',' minTypMax ')' { $$ = $1; } /* ignored */
| '#' '(' minTypMax ',' minTypMax ',' minTypMax ')' { $$ = $1; } /* ignored */
;
dlyTerm: yaID { $$ = NULL; }
@ -706,7 +706,9 @@ dlyTerm: yaID { $$ = NULL; }
| yaFLOATNUM { $$ = NULL; }
;
dlyInParen: dlyTerm { } /* ignored */
// IEEE: mintypmax_expression and constant_mintypmax_expression
minTypMax: expr { $$ = $1; } /* ignored */
| expr ':' expr ':' expr { $$ = $1; } /* ignored */
;
sigAndAttr: sigId sigAttrListE { $$ = $1; }