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Fix empty for blocks

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git-svn-id: file://localhost/svn/verilator/trunk/verilator@888 77ca24e4-aefa-0310-84f0-b9a241c72d87
This commit is contained in:
Wilson Snyder 2007-02-27 14:30:22 +00:00
parent bec3daa79f
commit bd264006ef
3 changed files with 26 additions and 6 deletions
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14
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@ -3,11 +3,15 @@ Revision history for Verilator
The contributors that suggested a given feature are shown in []. [by ...]
indicates the contributor was also the author of the fix; Thanks!
* Verilator 3.63**
**** Fix internal error when public for loop has empty body. [David Addison]
* Verilator 3.633 2/7/2007
*** Add --trace-depth option for minimizing VCD file size. [Emerson Suguimoto]
*** With VL_DEBUG, show wires causing convergance errors. [Mike Shinkarovsky]
*** With VL_DEBUG, show wires causing convergence errors. [Mike Shinkarovsky]
**** Fix isolate_assignments when many signals per always. [Mike Shinkarovsky]
@ -95,7 +99,7 @@ indicates the contributor was also the author of the fix; Thanks!
**** Removed coverage request variable; see Coverage limitations in docs.
**** Fix DOS carrage returns in multiline defines. [Ralf Karge]
**** Fix DOS carriage returns in multiline defines. [Ralf Karge]
**** Fix printf format warnings on 64-bit linux.
@ -107,7 +111,7 @@ indicates the contributor was also the author of the fix; Thanks!
*** Added --inhibit-sim flag for environments using old __Vm_inhibitSim.
*** Added `systemc_dtor for destructor extentions. [Allan Cochrane]
*** Added `systemc_dtor for destructor extensions. [Allan Cochrane]
*** Added -MP to make phony dependencies, ala GCC's.
@ -142,7 +146,7 @@ indicates the contributor was also the author of the fix; Thanks!
**** Fix extraneous UNSIGNED warning when comparing genvars. [David Hewson]
**** Fix extra whitespace in $display %c. [by David Addison]
**** Fix extra white space in $display %c. [by David Addison]
**** vl_finish and vl_fatal now print via VL_PRINTF rather then cerr/cout.
@ -245,7 +249,7 @@ indicates the contributor was also the author of the fix; Thanks!
**** Fix functions where regs are declared before inputs. [Danny Ding]
**** Fix bad deep expressions with bitselects and rotate. [Prabhat Gupta]
**** Fix bad deep expressions with bit-selects and rotate. [Prabhat Gupta]
* Verilator 3.500 10/30/2005 Stable

7
src/V3Unroll.cpp
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@ -252,7 +252,12 @@ private:
if (clonedIncsp) {
// Previous iteration of loop set the variable.
// This set is redundant with this next iteration and can be removed.
clonedIncsp->unlinkFrBack()->deleteTree();
if (clonedIncsp == newbodysp) { // Increment was only thing in list
newbodysp = NULL;
} else {
clonedIncsp->unlinkFrBack();
}
clonedIncsp->deleteTree();
}
clonedIncsp = incp->clonep(); if (!clonedIncsp) nodep->v3fatalSrc("inc failed");
}

11
test_regress/t/t_unroll_signed.v
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@ -11,6 +11,17 @@ module t (/*AUTOARG*/
input clk;
// Check empty blocks
task EmptyFor;
/* verilator public */
integer i;
begin
for (i = 0; i < 2; i = i+1)
begin
end
end
endtask
// Check look unroller
reg signed signed_tests_only = 1'sb1;
integer total;