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Fix handling user-botch of %d to print real.
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@ -741,6 +741,7 @@ vlsint32_t V3Number::toSInt() const {
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vluint64_t V3Number::toUQuad() const {
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UASSERT(!isFourState(), "toUQuad with 4-state "<<*this);
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// We allow wide numbers that represent values <= 64 bits
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if (isDouble()) return static_cast<vluint64_t>(toDouble());
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for (int i=2; i<words(); ++i) {
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if (m_value[i]) {
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v3error("Value too wide for 64-bits expected in this context "<<*this);
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@ -753,6 +754,7 @@ vluint64_t V3Number::toUQuad() const {
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}
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vlsint64_t V3Number::toSQuad() const {
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if (isDouble()) return static_cast<vlsint64_t>(toDouble());
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vluint64_t v = toUQuad();
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vluint64_t signExtend = (-(v & (VL_ULL(1)<<(width()-1))));
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vluint64_t extended = v | signExtend;
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@ -49,4 +49,5 @@ extra argument: 0000000000000000
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[0] Embedded <#013> return
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[0] Embedded
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multiline
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log10(2) = 2
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*-* All Finished *-*
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@ -139,6 +139,10 @@ multiline", $time);
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`ifndef NC // NC-Verilog 5.3 chokes on this test
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if (str !== 32'h00_bf_11_0a) $stop;
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`endif
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// $itord conversion bug, note a %d instead of proper float
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$display("log10(2) = %d", $log10(100));
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$write("*-* All Finished *-*\n");
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$finish;
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end
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