From bbb223f217c435ee2ae51379c7456fd6753215a8 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Thu, 11 Jul 2024 06:59:15 -0400
Subject: [PATCH] Fix error on empty generate with -O0 (#5250).

---
 Changes                            |  1 +
 src/V3Unroll.cpp                   |  6 +++++-
 test_regress/t/t_genfor_init_o0.pl | 20 ++++++++++++++++++++
 test_regress/t/t_genfor_init_o0.v  | 10 ++++++++++
 4 files changed, 36 insertions(+), 1 deletion(-)
 create mode 100755 test_regress/t/t_genfor_init_o0.pl
 create mode 100644 test_regress/t/t_genfor_init_o0.v

diff --git a/Changes b/Changes
index a985c0b76..788b82c30 100644
--- a/Changes
+++ b/Changes
@@ -22,6 +22,7 @@ Verilator 5.027 devel
 * Fix unknown conversion on queues (#5220). [Alex Solomatnikov]
 * Fix top-level unpacked structure resets (#5221).
 * Fix concurrency for mailbox and semaphores (#5222). [Liam Braun]
+* Fix error on empty generate with -O0 (#5250).
 
 
 Verilator 5.026 2024-06-15
diff --git a/src/V3Unroll.cpp b/src/V3Unroll.cpp
index 25eb43d89..6e5d55b7b 100644
--- a/src/V3Unroll.cpp
+++ b/src/V3Unroll.cpp
@@ -356,7 +356,11 @@ class UnrollVisitor final : public VNVisitor {
             }
         }
         if (!newbodysp) {  // initp might have effects after the loop
-            newbodysp = initp;  // Maybe nullptr
+            if (m_generate && initp) {  // GENFOR(ASSIGN(...)) need to move under a new Initial
+                newbodysp = new AstInitial{initp->fileline(), initp};
+            } else {
+                newbodysp = initp;  // Maybe nullptr
+            }
             initp = nullptr;
         }
         // Replace the FOR()
diff --git a/test_regress/t/t_genfor_init_o0.pl b/test_regress/t/t_genfor_init_o0.pl
new file mode 100755
index 000000000..60b075c18
--- /dev/null
+++ b/test_regress/t/t_genfor_init_o0.pl
@@ -0,0 +1,20 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(vlt => 1);
+
+compile(
+    verilator_flags2 => ['-O0'],
+    make_main => 0,
+    verilator_make_gmake => 0,
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_genfor_init_o0.v b/test_regress/t/t_genfor_init_o0.v
new file mode 100644
index 000000000..ec334dc9a
--- /dev/null
+++ b/test_regress/t/t_genfor_init_o0.v
@@ -0,0 +1,10 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2024 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+module t(/*AUTOARG*/);
+   genvar i;
+   for (i = 0; i < 0; i = i + 1) begin end
+endmodule