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Fix typedefs pointing to parameterized classes (#4747)
* Skip handling of ClassOrPackageRef nodes that point to Typedefs
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@ -1150,7 +1150,12 @@ class ParamVisitor final : public VNVisitor {
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if (nodep->ifacep()) visitCellOrClassRef(nodep, true);
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}
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void visit(AstClassRefDType* nodep) override { visitCellOrClassRef(nodep, false); }
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void visit(AstClassOrPackageRef* nodep) override { visitCellOrClassRef(nodep, false); }
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void visit(AstClassOrPackageRef* nodep) override {
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// If it points to a typedef it is not really a class reference. That typedef will be
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// visited anyway (from its parent node), so even if it points to a parameterized class
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// type, the instance will be created.
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if (!VN_IS(nodep->classOrPackageNodep(), Typedef)) visitCellOrClassRef(nodep, false);
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}
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// Make sure all parameters are constantified
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void visit(AstVar* nodep) override {
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21
test_regress/t/t_class_param_typedef2.pl
Executable file
21
test_regress/t/t_class_param_typedef2.pl
Executable file
@ -0,0 +1,21 @@
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#!/usr/bin/env perl
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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2022 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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scenarios(simulator => 1);
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compile(
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);
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execute(
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check_finished => 1,
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);
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ok(1);
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1;
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34
test_regress/t/t_class_param_typedef2.v
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34
test_regress/t/t_class_param_typedef2.v
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@ -0,0 +1,34 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2023 by Antmicro Ltd.
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// SPDX-License-Identifier: CC0-1.0
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virtual class Virt;
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endclass
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class MyInt;
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int x;
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endclass
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class uvm_object_registry #(
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type T = Virt
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);
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static function T create_object();
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T obj = new();
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obj.x = 1;
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return obj;
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endfunction
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endclass
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typedef uvm_object_registry#(MyInt) type_id;
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module t;
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initial begin
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MyInt mi = type_id::create_object();
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if (mi.x != 1) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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