From b4d4917c6cc732479ccf573dfedfea57d7b1d883 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Sat, 30 Sep 2006 00:08:09 +0000 Subject: [PATCH] Fix coredump in XREFs under FUNCREF's git-svn-id: file://localhost/svn/verilator/trunk/verilator@800 77ca24e4-aefa-0310-84f0-b9a241c72d87 --- Changes | 2 ++ bin/verilator | 12 ++++++------ src/V3Inline.cpp | 1 + test_regress/t/t_func_dotted.v | 30 ++++++++++++++++++++++++++++-- 4 files changed, 37 insertions(+), 8 deletions(-) diff --git a/Changes b/Changes index 119c45f24..0d7218c5e 100644 --- a/Changes +++ b/Changes @@ -16,6 +16,8 @@ indicates the contributor was also the author of the fix; Thanks! **** Optimize additional boolean identities (a|a = a, etc.) +**** Fix coredump when dotted cross-ref inside task call. [Eugene Weber] + * Verilator 3.610 09/20/2006 *** Verilator now works under DJGPP (Pentium GCC). [John Stroebel] diff --git a/bin/verilator b/bin/verilator index 94681f84b..249cd83c6 100755 --- a/bin/verilator +++ b/bin/verilator @@ -169,7 +169,7 @@ sub run { warn "%Error: export VERILATOR_ROOT=$ENV{VERILATOR_ROOT}\n"; warn "%Error: $command\n"; } - die "%Error: Command Failed $command, $status, stopped"; + die "%Error: Command Failed $command\n"; } } @@ -283,8 +283,8 @@ the comment "DefaultClock": =item --debug -Select the debug built image of Verilator (if available), and enable -debugging messages and intermediate form dump files. +Select the debug built image of Verilator (if available), and enable more +internal assertions, debugging messages, and intermediate form dump files. =item -E @@ -1623,7 +1623,7 @@ outputs. Now, the following should fail: cd test_regress t/t_BUG.pl -Finally, Mail the bug report to C +Finally, Mail the bug report to C. =head1 HISTORY @@ -1650,8 +1650,8 @@ scratch in C++. This added many optimizations, yielding about a 2-5x performance gain. Currently, various language features and performance enhancements are added -as the need arises. Verilator is now about 2x faster then in 2002, and -as fast as most popular commercial simulators. +as the need arises. Verilator is now about 2x faster then in 2002, and is +faster then many popular commercial simulators. =head1 CONTRIBUTORS diff --git a/src/V3Inline.cpp b/src/V3Inline.cpp index 4064d1784..f39cdcce0 100644 --- a/src/V3Inline.cpp +++ b/src/V3Inline.cpp @@ -353,6 +353,7 @@ private: virtual void visit(AstNodeFTaskRef* nodep, AstNUser*) { // Cleanup link until V3LinkDot can correct it nodep->taskp(NULL); + nodep->iterateChildren(*this); } // Nop's to speed up the loop virtual void visit(AstAlways* nodep, AstNUser*) { diff --git a/test_regress/t/t_func_dotted.v b/test_regress/t/t_func_dotted.v index ddb46375c..789b5335e 100644 --- a/test_regress/t/t_func_dotted.v +++ b/test_regress/t/t_func_dotted.v @@ -37,6 +37,11 @@ module t (/*AUTOARG*/ if (ma0.mb0.mc0.getP3(1'b0) !== 32'h0) $stop; if (ma0.mb0.mc1.getP3(1'b0) !== 32'h1) $stop; end + if (cyc==5) begin + ma0. checkName(ma0. getName(1'b0)); + ma0.mb0. checkName(ma0.mb0. getName(1'b0)); + ma0.mb0.mc0.checkName(ma0.mb0.mc0.getName(1'b0)); + end if (cyc==9) begin $write("*-* All Finished *-*\n"); $finish; @@ -72,7 +77,9 @@ module ma (); `INLINE_MODULE mb #(0) mb0 (); + reg [31:0] gName; initial gName = "ma "; function [31:0] getName; input fake; getName = "ma "; endfunction + task checkName; input [31:0] name; if (name !== "ma ") $stop; endtask initial begin if (ma.getName(1'b0) !== "ma ") $stop; @@ -89,13 +96,23 @@ module mb (); mc #(P2,1) mc1 (); global_mod #(32'hf33d) global_cell2 (); + reg [31:0] gName; initial gName = "mb "; function [31:0] getName; input fake; getName = "mb "; endfunction function [31:0] getP2 ; input fake; getP2 = P2; endfunction + task checkName; input [31:0] name; if (name !== "mb ") $stop; endtask initial begin - if (ma.getName(1'b0) !== "ma ") $stop; - if (getName(1'b0) !== "mb ") $stop; +`ifndef verilator #1; `endif + if (ma. getName(1'b0) !== "ma ") $stop; + if ( getName(1'b0) !== "mb ") $stop; if (mc1.getName(1'b0) !== "mc ") $stop; + + ma. checkName (ma. gName); + /**/checkName ( gName); + mc1.checkName (mc1.gName); + ma. checkName (ma. getName(1'b0)); + /**/checkName ( getName(1'b0)); + mc1.checkName (mc1.getName(1'b0)); end endmodule @@ -104,12 +121,21 @@ module mc (); parameter P2 = 0; parameter P3 = 0; + reg [31:0] gName; initial gName = "mc "; function [31:0] getName; input fake; getName = "mc "; endfunction function [31:0] getP3 ; input fake; getP3 = P3; endfunction + task checkName; input [31:0] name; if (name !== "mc ") $stop; endtask initial begin +`ifndef verilator #1; `endif if (ma.getName(1'b0) !== "ma ") $stop; if (mb.getName(1'b0) !== "mb ") $stop; if (mc.getName(1'b0) !== "mc ") $stop; + ma.checkName (ma.gName); + mb.checkName (mb.gName); + mc.checkName (mc.gName); + ma.checkName (ma.getName(1'b0)); + mb.checkName (mb.getName(1'b0)); + mc.checkName (mc.getName(1'b0)); end endmodule