From b3e2d26e3536039c1884e64f8f3dbf99f0ef3bb5 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Wed, 12 Jun 2019 22:22:36 -0400
Subject: [PATCH] Tests: Remove tabs from golden-output tests. No functional
 change.

---
 test_regress/t/t_array_list_bad.v        |  6 +-
 test_regress/t/t_case_default_bad.v      |  6 +-
 test_regress/t/t_case_genx_bad.v         |  6 +-
 test_regress/t/t_case_x_bad.v            |  8 +--
 test_regress/t/t_case_zx_bad.v           |  6 +-
 test_regress/t/t_cdc_async_bad.v         | 14 ++---
 test_regress/t/t_delay.v                 | 12 ++--
 test_regress/t/t_display.v               | 60 +++++++++----------
 test_regress/t/t_display_signed.v        | 12 ++--
 test_regress/t/t_display_wide.v          | 20 +++----
 test_regress/t/t_enum_overlap_bad.v      |  8 +--
 test_regress/t/t_func_bad.v              |  4 +-
 test_regress/t/t_func_const_struct_bad.v |  6 +-
 test_regress/t/t_gen_cond_bitrange_bad.v | 32 +++++-----
 test_regress/t/t_gen_upscope.v           | 10 ++--
 test_regress/t/t_initial_dlyass.v        |  8 +--
 test_regress/t/t_inst_overwide.v         | 22 +++----
 test_regress/t/t_interface_missing_bad.v |  4 +-
 test_regress/t/t_interface_typo_bad.v    |  4 +-
 test_regress/t/t_lint_always_comb_bad.v  | 14 ++---
 test_regress/t/t_lint_blksync_bad.v      | 12 ++--
 test_regress/t/t_lint_pindup_bad.v       |  6 +-
 test_regress/t/t_lint_setout_bad.v       |  8 +--
 test_regress/t/t_lint_syncasyncnet_bad.v | 14 ++---
 test_regress/t/t_lint_width_bad.v        | 14 ++---
 test_regress/t/t_mem_multi_ref_bad.v     | 20 +++----
 test_regress/t/t_order_clkinst.v         | 50 ++++++++--------
 test_regress/t/t_order_loop_bad.v        |  6 +-
 test_regress/t/t_param_concat.v          | 10 ++--
 test_regress/t/t_select_bad_range2.v     |  4 +-
 test_regress/t/t_struct_init.v           | 58 +++++++++---------
 test_regress/t/t_udp.v                   | 45 +++++++-------
 test_regress/t/t_udp_bad.out             |  2 +-
 test_regress/t/t_unopt_combo.v           | 76 ++++++++++++------------
 test_regress/t/t_var_nonamebegin.v       | 70 +++++++++++-----------
 test_regress/t/t_var_rsvd_port.v         |  6 +-
 test_regress/t/t_var_types_bad.v         | 68 ++++++++++-----------
 37 files changed, 364 insertions(+), 367 deletions(-)

diff --git a/test_regress/t/t_array_list_bad.v b/test_regress/t/t_array_list_bad.v
index 25c115c78..50f2f0004 100644
--- a/test_regress/t/t_array_list_bad.v
+++ b/test_regress/t/t_array_list_bad.v
@@ -5,9 +5,9 @@
 
 package pkg;
    typedef struct packed {
-      logic 	  t1;
-      logic 	  t2;
-      logic 	  t3;
+      logic       t1;
+      logic       t2;
+      logic       t3;
    } type_t;
 endpackage : pkg
 
diff --git a/test_regress/t/t_case_default_bad.v b/test_regress/t/t_case_default_bad.v
index 3bf779978..882d24ca0 100644
--- a/test_regress/t/t_case_default_bad.v
+++ b/test_regress/t/t_case_default_bad.v
@@ -10,9 +10,9 @@ module t (/*AUTOARG*/
    input [3:0] value;
    always @ (/*AS*/value) begin
       case (value)
-	default: $stop;
-	4'd0000: $stop;
-	default: $stop;
+        default: $stop;
+        4'd0000: $stop;
+        default: $stop;
       endcase
    end
 endmodule
diff --git a/test_regress/t/t_case_genx_bad.v b/test_regress/t/t_case_genx_bad.v
index 0b1411e82..b09bea3e4 100644
--- a/test_regress/t/t_case_genx_bad.v
+++ b/test_regress/t/t_case_genx_bad.v
@@ -9,9 +9,9 @@ module t (/*AUTOARG*/);
 
    generate
       case (P)
-	32'b0:    initial begin end
-	32'b1xxx: initial begin end
-	default:  initial begin end
+        32'b0:    initial begin end
+        32'b1xxx: initial begin end
+        default:  initial begin end
       endcase
    endgenerate
 
diff --git a/test_regress/t/t_case_x_bad.v b/test_regress/t/t_case_x_bad.v
index 126a88d37..b2662f7c7 100644
--- a/test_regress/t/t_case_x_bad.v
+++ b/test_regress/t/t_case_x_bad.v
@@ -11,12 +11,12 @@ module t (/*AUTOARG*/
    input [3:0] value;
    always @ (/*AS*/value) begin
       casex (value)
-	default: $stop;
+        default: $stop;
       endcase
       case (value)
-	4'b0000: $stop;
-	4'b1xxx: $stop;
-	default: $stop;
+        4'b0000: $stop;
+        4'b1xxx: $stop;
+        default: $stop;
       endcase
    end
 
diff --git a/test_regress/t/t_case_zx_bad.v b/test_regress/t/t_case_zx_bad.v
index 661602a0e..1ba42561b 100644
--- a/test_regress/t/t_case_zx_bad.v
+++ b/test_regress/t/t_case_zx_bad.v
@@ -11,9 +11,9 @@ module t (/*AUTOARG*/
    input [3:0] value;
    always @ (/*AS*/value) begin
       casez (value)
-	4'b0000: $stop;
-	4'b1xxx: $stop;
-	default: $stop;
+        4'b0000: $stop;
+        4'b1xxx: $stop;
+        default: $stop;
       endcase
    end
 
diff --git a/test_regress/t/t_cdc_async_bad.v b/test_regress/t/t_cdc_async_bad.v
index f7d4c96d5..98f1355be 100644
--- a/test_regress/t/t_cdc_async_bad.v
+++ b/test_regress/t/t_cdc_async_bad.v
@@ -18,7 +18,7 @@ module t (/*AUTOARG*/
    Flop flop0 (.q(q0), .rst_n(rst0_n), .clk(clk), .d(d));
 
    // OK -- from flop
-   reg 	 rst1_n;
+   reg   rst1_n;
    always @ (posedge clk) rst1_n <= rst0_n;
    output wire  q1;
    Flop flop1 (.q(q1), .rst_n(rst1_n), .clk(clk), .d(d));
@@ -64,10 +64,10 @@ module t (/*AUTOARG*/
 endmodule
 
 module Flop (
-	     input clk,
-	     input d,
-	     input rst_n,
-	     output q);
+             input clk,
+             input d,
+             input rst_n,
+             output q);
 
    always @ (posedge clk or negedge rst_n) begin
       if (!rst_n) q <= 1'b0;
@@ -76,6 +76,6 @@ module Flop (
 endmodule
 
 module Sub (input a, b,
-	    output z);
-   wire 	   z = a|b;
+            output z);
+   wire            z = a|b;
 endmodule
diff --git a/test_regress/t/t_delay.v b/test_regress/t/t_delay.v
index 2c2f33686..3b41e419c 100644
--- a/test_regress/t/t_delay.v
+++ b/test_regress/t/t_delay.v
@@ -21,16 +21,16 @@ module t (/*AUTOARG*/
    always @ (posedge clk) begin
       cyc <= cyc + 1;
       if (cyc==1) begin
-	 dly0 <= #0 32'h11;
+         dly0 <= #0 32'h11;
       end
       else if (cyc==2) begin
-	 dly0 <= #0.12 dly0 + 32'h12;
+         dly0 <= #0.12 dly0 + 32'h12;
       end
       else if (cyc==3) begin
-	 if (dly0 !== 32'h23) $stop;
-	 if (dly2 !== 32'h25) $stop;
-	 $write("*-* All Finished *-*\n");
-	 #100 $finish;
+         if (dly0 !== 32'h23) $stop;
+         if (dly2 !== 32'h25) $stop;
+         $write("*-* All Finished *-*\n");
+         #100 $finish;
       end
    end
 
diff --git a/test_regress/t/t_display.v b/test_regress/t/t_display.v
index cd85e045e..87fff05bf 100644
--- a/test_regress/t/t_display.v
+++ b/test_regress/t/t_display.v
@@ -67,25 +67,25 @@ module t;
 
       // Display formatting
       $display("[%0t] %%b=%b %%0b=%0b  %%b=%b %%0b=%0b  %%b=%b %%0b=%0b", $time,
-	       nine, nine, quad, quad, wide, wide);
+               nine, nine, quad, quad, wide, wide);
       $display("[%0t] %%B=%B %%0B=%0B  %%B=%B %%0B=%0B  %%B=%B %%0B=%0B", $time,
-	       nine, nine, quad, quad, wide, wide);
+               nine, nine, quad, quad, wide, wide);
       $display("[%0t] %%d=%d %%0d=%0d  %%d=%d %%0d=%0d  %%d=%d %%0d=%0d", $time,
                nine, nine, quad, quad, wide, wide);
       $display("[%0t] %%D=%D %%0D=%0D  %%D=%D %%0D=%0D  %%D=%D %%0D=%0D", $time,
                nine, nine, quad, quad, wide, wide);
       $display("[%0t] %%h=%h %%0h=%0h  %%h=%h %%0h=%0h  %%h=%h %%0h=%0h", $time,
-	       nine, nine, quad, quad, wide, wide);
+               nine, nine, quad, quad, wide, wide);
       $display("[%0t] %%H=%H %%0H=%0H  %%H=%H %%0H=%0H  %%H=%H %%0H=%0H", $time,
-	       nine, nine, quad, quad, wide, wide);
+               nine, nine, quad, quad, wide, wide);
       $display("[%0t] %%o=%o %%0o=%0o  %%o=%o %%0o=%0o  %%o=%o %%0o=%0o", $time,
-	       nine, nine, quad, quad, wide, wide);
+               nine, nine, quad, quad, wide, wide);
       $display("[%0t] %%O=%O %%0O=%0O  %%O=%O %%0O=%0O  %%O=%O %%0O=%0o", $time,
-	       nine, nine, quad, quad, wide, wide);
+               nine, nine, quad, quad, wide, wide);
       $display("[%0t] %%x=%x %%0x=%0x  %%x=%x %%0x=%0x  %%x=%x %%0x=%0x", $time,
-	       nine, nine, quad, quad, wide, wide);
+               nine, nine, quad, quad, wide, wide);
       $display("[%0t] %%X=%X %%0X=%0X  %%X=%X %%0X=%0X  %%X=%X %%0X=%0X", $time,
-	       nine, nine, quad, quad, wide, wide);
+               nine, nine, quad, quad, wide, wide);
 
       $display("[%0t] %%d=%d %%0d=%0d  %%d=%d %%0d=%0d  %%d=%d %%0d=%0d", $time,
                nines, nines, quads, quads, wides, wides);
@@ -94,39 +94,39 @@ module t;
       //
       // verilator lint_off WIDTH
       $display("[%0t] %%C=%C %%0C=%0C", $time,
-	       "a"+nine, "a"+nine);
+               "a"+nine, "a"+nine);
       $display("[%0t] %%c=%c %%0c=%0c", $time,
-	       "a"+nine, "a"+nine);
+               "a"+nine, "a"+nine);
       // verilator lint_on WIDTH
 
       $display("[%0t] %%v=%v %%0v=%0v  %%v=%v %%0v=%0v  %%v=%v %%0v=%0v <", $time,
-	       nine, nine, quad, quad, wide, wide);
+               nine, nine, quad, quad, wide, wide);
       $display("[%0t] %%V=%V %%0V=%0V  %%V=%V %%0V=%0V  %%V=%V %%0V=%0V <", $time,
-	       nine, nine, quad, quad, wide, wide);
+               nine, nine, quad, quad, wide, wide);
       $display("[%0t] %%p=%p %%0p=%0p  %%p=%p %%0p=%0p  %%p=%p %%0p=%0p", $time,
-	       nine, nine, quad, quad, wide, wide);
+               nine, nine, quad, quad, wide, wide);
       $display("[%0t] %%P=%P %%0P=%0P  %%P=%P %%0P=%0P  %%P=%P %%0P=%0P", $time,
-	       nine, nine, quad, quad, wide, wide);
+               nine, nine, quad, quad, wide, wide);
       $display("[%0t] %%P=%P", $time,
-	       svs);
+               svs);
 
       $display("[%0t] %%u=%u %%0u=%0u", $time,
-	       {"a","b","c","d"}, {"a","b","c","d"});  // Avoid binary output
+               {"a","b","c","d"}, {"a","b","c","d"});  // Avoid binary output
       $display("[%0t] %%U=%U %%0U=%0U", $time,
-	       {"a","b","c","d"}, {"a","b","c","d"});  // Avoid binary output
+               {"a","b","c","d"}, {"a","b","c","d"});  // Avoid binary output
       // %z is tested in t_sys_sformat.v
 
       $display("[%0t] %%D=%D %%d=%d %%01d=%01d %%06d=%06d %%6d=%6d", $time,
-	       nine, nine, nine, nine, nine);
+               nine, nine, nine, nine, nine);
       $display("[%0t] %%t=%t %%03t=%03t %%0t=%0t", $time,
-	       $time, $time, $time);
+               $time, $time, $time);
       $display;
       // Not testing %0s, it does different things in different simulators
       $display("[%0t] %%s=%s %%s=%s %%s=%s", $time,
-	       str2[7:0], str2, str3);
+               str2[7:0], str2, str3);
 
       $display("[%0t] %s%s%s", $time,
-	       "hel", "lo, fr", "om a very long string. Percent %s are literally substituted in.");
+               "hel", "lo, fr", "om a very long string. Percent %s are literally substituted in.");
       $display("hel", "lo, fr", "om a concatenated string.");
       $write("hel", "lo, fr", "om a concatenated format string [%0t].\n", $time);
       $display("extra argument: ", $time);
@@ -136,7 +136,7 @@ module t;
 multiline", $time);
 
       // Str check
-`ifndef NC	// NC-Verilog 5.3 chokes on this test
+`ifndef NC      // NC-Verilog 5.3 chokes on this test
       if (str !== 32'h00_bf_11_0a) $stop;
 `endif
       $write("*-* All Finished *-*\n");
@@ -147,10 +147,10 @@ endmodule
 module sub;
    task write_m;
       begin
-	 $write("[%0t] In %m (%l)\n", $time);
-	 begin : subblock
-	    $write("[%0t] In %M (%L)\n", $time); // Uppercase %M test
-	 end
+         $write("[%0t] In %m (%l)\n", $time);
+         begin : subblock
+            $write("[%0t] In %M (%L)\n", $time); // Uppercase %M test
+         end
       end
    endtask
 endmodule
@@ -159,10 +159,10 @@ module sub2;
    // verilator no_inline_module
    task write_m;
       begin
-	 $write("[%0t] In %m (%l)\n", $time);
-	 begin : subblock2
-	    $write("[%0t] In %m (%L)\n", $time);
-	 end
+         $write("[%0t] In %m (%l)\n", $time);
+         begin : subblock2
+            $write("[%0t] In %m (%L)\n", $time);
+         end
       end
    endtask
 endmodule
diff --git a/test_regress/t/t_display_signed.v b/test_regress/t/t_display_signed.v
index c7b29c5f9..1db324fa9 100644
--- a/test_regress/t/t_display_signed.v
+++ b/test_regress/t/t_display_signed.v
@@ -14,17 +14,17 @@ module t;
    initial begin
       // Display formatting
       $display("[%0t] lp %%x=%x %%x=%x %%o=%o %%b=%b %%0d=%0d %%d=%d", $time,
-	       longp, longp, longp, longp, longp, longp);
+               longp, longp, longp, longp, longp, longp);
       $display("[%0t] ln %%x=%x %%x=%x %%o=%o %%b=%b %%0d=%0d %%d=%d", $time,
-	       longn, longn, longn, longn, longn, longn);
+               longn, longn, longn, longn, longn, longn);
       $display("[%0t] qp %%x=%x %%x=%x %%o=%o %%b=%b %%0d=%0d %%d=%d", $time,
-	       quadp, quadp, quadp, quadp, quadp, quadp);
+               quadp, quadp, quadp, quadp, quadp, quadp);
       $display("[%0t] qn %%x=%x %%x=%x %%o=%o %%b=%b %%0d=%0d %%d=%d", $time,
-	       quadn, quadn, quadn, quadn, quadn, quadn);
+               quadn, quadn, quadn, quadn, quadn, quadn);
       $display("[%0t] wp %%x=%x %%x=%x %%o=%o %%b=%b", $time,
-	       widep, widep, widep, widep);
+               widep, widep, widep, widep);
       $display("[%0t] wn %%x=%x %%x=%x %%o=%o %%b=%b", $time,
-	       widen, widen, widen, widen);
+               widen, widen, widen, widen);
       $display;
       $write("*-* All Finished *-*\n");
       $finish;
diff --git a/test_regress/t/t_display_wide.v b/test_regress/t/t_display_wide.v
index b7c16976d..0e583b5af 100644
--- a/test_regress/t/t_display_wide.v
+++ b/test_regress/t/t_display_wide.v
@@ -9,7 +9,7 @@ module t (/*AUTOARG*/
    );
    input clk;
 
-   integer 	cyc=0;
+   integer      cyc=0;
    reg [4095:0] crc;
 
    // Test loop
@@ -17,17 +17,17 @@ module t (/*AUTOARG*/
       cyc <= cyc + 1;
       crc <= {crc[4094:0], crc[63]^crc[2]^crc[0]};  // not a good crc :)
       if (cyc==0) begin
-	 // Setup
-	 crc <= 4096'h9f51804b5275c7b6ab9907144a58649bb778f9718062fa5c336fcc9edcad7cf17aad0a656244017bb21d9f97f7c0c147b6fa7488bb9d5bb8d3635b20fba1deab597121c502b21f49b18da998852d29a6b2b649315a3323a31e7e5f41e9bbb7e44046467438f37694857b963250bdb137a922cfce2af1defd1f93db5aa167f316d751bb274bda96fdee5e2c6eb21886633246b165341f0594c27697b06b62b1ad05ebe3c08909a54272de651296dcdd3d1774fc432d22210d8f6afa50b02cf23336f8cc3a0a2ebfd1a3a60366a1b66ef346e0379116d68caa01279ac2772d1f3cd76d2cbbc68ada6f83ec2441b2679b405486df8aa734ea1729b40c3f82210e8e42823eb3fd6ca77ee19f285741c4e8bac1ab7855c3138e84b6da1d897bbe37faf2d0256ad2f7ff9e704a63d824c1e97bddce990cae1578f9537ae2328d0afd69ffb317cbcf859696736e45e5c628b44727557c535a7d02c07907f2dccd6a21ca9ae9e1dbb1a135a8ebc2e0aa8c7329b898d02896273defe21beaa348e11165b71c48cf1c09714942a5a2ddc2adcb6e42c0f630117ee21205677d5128e8efc18c9a6f82a8475541fd722cca2dd829b7e78fef89dbeab63ab7b849910eb4fe675656c4b42b9452c81a4ca6296190a81dc63e6adfaa31995d7dfe3438ee9df66488d6cf569380569ffe6e5ea313d23af6ff08d979af29374ee9aff1fa143df238a1;
+         // Setup
+         crc <= 4096'h9f51804b5275c7b6ab9907144a58649bb778f9718062fa5c336fcc9edcad7cf17aad0a656244017bb21d9f97f7c0c147b6fa7488bb9d5bb8d3635b20fba1deab597121c502b21f49b18da998852d29a6b2b649315a3323a31e7e5f41e9bbb7e44046467438f37694857b963250bdb137a922cfce2af1defd1f93db5aa167f316d751bb274bda96fdee5e2c6eb21886633246b165341f0594c27697b06b62b1ad05ebe3c08909a54272de651296dcdd3d1774fc432d22210d8f6afa50b02cf23336f8cc3a0a2ebfd1a3a60366a1b66ef346e0379116d68caa01279ac2772d1f3cd76d2cbbc68ada6f83ec2441b2679b405486df8aa734ea1729b40c3f82210e8e42823eb3fd6ca77ee19f285741c4e8bac1ab7855c3138e84b6da1d897bbe37faf2d0256ad2f7ff9e704a63d824c1e97bddce990cae1578f9537ae2328d0afd69ffb317cbcf859696736e45e5c628b44727557c535a7d02c07907f2dccd6a21ca9ae9e1dbb1a135a8ebc2e0aa8c7329b898d02896273defe21beaa348e11165b71c48cf1c09714942a5a2ddc2adcb6e42c0f630117ee21205677d5128e8efc18c9a6f82a8475541fd722cca2dd829b7e78fef89dbeab63ab7b849910eb4fe675656c4b42b9452c81a4ca6296190a81dc63e6adfaa31995d7dfe3438ee9df66488d6cf569380569ffe6e5ea313d23af6ff08d979af29374ee9aff1fa143df238a1;
       end
       else if (cyc==99) begin
-	 $write("[%0t] cyc==%0d crc=%x%x%x%x\n",$time, cyc, crc[4095:3072], crc[2071:2048], crc[2047:1024], crc[1023:0]);
-	 $write("[%0t] cyc==%0d crc=%b%b%b%b\n",$time, cyc, crc[4095:3072], crc[2071:2048], crc[2047:1024], crc[1023:0]);
-	 //Unsupported: $write("[%0t] cyc==%0d crc=%x\n",$time, cyc, crc);
-	 if (crc != 4096'h2961926edde3e5c6018be970cdbf327b72b5f3c5eab42995891005eec8767e5fdf03051edbe9d222ee756ee34d8d6c83ee877aad65c487140ac87d26c636a66214b4a69acad924c568cc8e8c79f97d07a6eedf91011919d0e3cdda5215ee58c942f6c4dea48b3f38abc77bf47e4f6d6a859fcc5b5d46ec9d2f6a5bf7b978b1bac862198cc91ac594d07c165309da5ec1ad8ac6b417af8f0224269509cb79944a5b7374f45dd3f10cb48884363dabe942c0b3c8ccdbe330e828baff468e980d9a86d9bbcd1b80de445b5a32a8049e6b09dcb47cf35db4b2ef1a2b69be0fb09106c99e6d01521b7e2a9cd3a85ca6d030fe08843a390a08facff5b29dfb867ca15d0713a2eb06ade1570c4e3a12db687625eef8dfebcb4095ab4bdffe79c1298f609307a5ef773a6432b855e3e54deb88ca342bf5a7fecc5f2f3e165a59cdb9179718a2d11c9d55f14d69f40b01e41fcb7335a8872a6ba7876ec684d6a3af0b82aa31cca6e26340a2589cf7bf886faa8d23844596dc71233c7025c5250a968b770ab72db90b03d8c045fb8848159df544a3a3bf063269be0aa11d5507f5c8b328b760a6df9e3fbe276faad8eadee126443ad3f99d595b12d0ae514b20693298a58642a07718f9ab7ea8c66575f7f8d0e3ba77d992235b3d5a4e015a7ff9b97a8c4f48ebdbfc2365e6bca4dd3ba6bfc7e850f7c8e2842c717a1d85a977a033f564fc
-	     ) $stop;
-	 $write("*-* All Finished *-*\n");
-	 $finish;
+         $write("[%0t] cyc==%0d crc=%x%x%x%x\n",$time, cyc, crc[4095:3072], crc[2071:2048], crc[2047:1024], crc[1023:0]);
+         $write("[%0t] cyc==%0d crc=%b%b%b%b\n",$time, cyc, crc[4095:3072], crc[2071:2048], crc[2047:1024], crc[1023:0]);
+         //Unsupported: $write("[%0t] cyc==%0d crc=%x\n",$time, cyc, crc);
+         if (crc != 4096'h2961926edde3e5c6018be970cdbf327b72b5f3c5eab42995891005eec8767e5fdf03051edbe9d222ee756ee34d8d6c83ee877aad65c487140ac87d26c636a66214b4a69acad924c568cc8e8c79f97d07a6eedf91011919d0e3cdda5215ee58c942f6c4dea48b3f38abc77bf47e4f6d6a859fcc5b5d46ec9d2f6a5bf7b978b1bac862198cc91ac594d07c165309da5ec1ad8ac6b417af8f0224269509cb79944a5b7374f45dd3f10cb48884363dabe942c0b3c8ccdbe330e828baff468e980d9a86d9bbcd1b80de445b5a32a8049e6b09dcb47cf35db4b2ef1a2b69be0fb09106c99e6d01521b7e2a9cd3a85ca6d030fe08843a390a08facff5b29dfb867ca15d0713a2eb06ade1570c4e3a12db687625eef8dfebcb4095ab4bdffe79c1298f609307a5ef773a6432b855e3e54deb88ca342bf5a7fecc5f2f3e165a59cdb9179718a2d11c9d55f14d69f40b01e41fcb7335a8872a6ba7876ec684d6a3af0b82aa31cca6e26340a2589cf7bf886faa8d23844596dc71233c7025c5250a968b770ab72db90b03d8c045fb8848159df544a3a3bf063269be0aa11d5507f5c8b328b760a6df9e3fbe276faad8eadee126443ad3f99d595b12d0ae514b20693298a58642a07718f9ab7ea8c66575f7f8d0e3ba77d992235b3d5a4e015a7ff9b97a8c4f48ebdbfc2365e6bca4dd3ba6bfc7e850f7c8e2842c717a1d85a977a033f564fc
+             ) $stop;
+         $write("*-* All Finished *-*\n");
+         $finish;
       end
    end
 endmodule
diff --git a/test_regress/t/t_enum_overlap_bad.v b/test_regress/t/t_enum_overlap_bad.v
index bc3b8a25d..00c84f7de 100644
--- a/test_regress/t/t_enum_overlap_bad.v
+++ b/test_regress/t/t_enum_overlap_bad.v
@@ -6,10 +6,10 @@
 module t (/*AUTOARG*/);
 
    enum { e0,
-	  e1,
-	  e2,
-	  e1b=1
-	  } BAD1;
+          e1,
+          e2,
+          e1b=1
+          } BAD1;
 
    initial begin
       $stop;
diff --git a/test_regress/t/t_func_bad.v b/test_regress/t/t_func_bad.v
index 7ced7e832..4ed56fa43 100644
--- a/test_regress/t/t_func_bad.v
+++ b/test_regress/t/t_func_bad.v
@@ -6,7 +6,7 @@
 module t;
    initial begin
       if (add(3'd1) != 0) $stop;  // Too few args
-      if (add(3'd1, 3'd2, 3'd3) != 0) $stop;	// Too many args
+      if (add(3'd1, 3'd2, 3'd3) != 0) $stop;    // Too many args
       x; // Too few args
       if (hasout(3'd1) != 0) $stop;  // outputs
       //
@@ -19,7 +19,7 @@ module t;
       input [2:0] from1;
       input [2:0] from2;
       begin
-	 add = from1 + from2;
+         add = from1 + from2;
       end
    endfunction
 
diff --git a/test_regress/t/t_func_const_struct_bad.v b/test_regress/t/t_func_const_struct_bad.v
index 722ffab47..c87514e26 100644
--- a/test_regress/t/t_func_const_struct_bad.v
+++ b/test_regress/t/t_func_const_struct_bad.v
@@ -31,9 +31,9 @@ module t;
    function integer f_add2(input [31:0] a, input [31:0] b, input [31:0] c);
       params_t params;
       params = '{
-		 a: a,
-		 b: b
-		 };
+                 a: a,
+                 b: b
+                 };
       f_add2 = f_add(params)+c;
    endfunction
 endmodule
diff --git a/test_regress/t/t_gen_cond_bitrange_bad.v b/test_regress/t/t_gen_cond_bitrange_bad.v
index bc20eb441..90b785667 100644
--- a/test_regress/t/t_gen_cond_bitrange_bad.v
+++ b/test_regress/t/t_gen_cond_bitrange_bad.v
@@ -56,24 +56,24 @@ module test_gen
 
       for (g = 0; g < `MAX_SIZE; g = g + 1) begin
          if ((g < (SIZE + 1)) && MASK[g]) begin
-	    always @(posedge clk) begin
+            always @(posedge clk) begin
 `ifdef TEST_VERBOSE
-	       $write ("Logical AND generate if MASK [%1d] = %d\n", g, MASK[g]);
+               $write ("Logical AND generate if MASK [%1d] = %d\n", g, MASK[g]);
 `endif
-	    end
-	 end
+            end
+         end
       end
    endgenerate
 
    generate
       for (g = 0; g < `MAX_SIZE; g = g + 1) begin
          if ((g < SIZE) && MASK[g + 1]) begin
-	    always @(posedge clk) begin
+            always @(posedge clk) begin
 `ifdef TEST_VERBOSE
-	       $write ("Logical AND generate if MASK [%1d] = %d\n", g, MASK[g]);
+               $write ("Logical AND generate if MASK [%1d] = %d\n", g, MASK[g]);
 `endif
-	    end
-	 end
+            end
+         end
       end
    endgenerate
 
@@ -81,12 +81,12 @@ module test_gen
    generate
       for (g = 0; g < `MAX_SIZE; g = g + 1) begin
          if ((g < (SIZE)) & MASK[g]) begin
-	    always @(posedge clk) begin
+            always @(posedge clk) begin
 `ifdef TEST_VERBOSE
-	       $write ("Bitwise AND generate if MASK [%1d] = %d\n", g, MASK[g]);
+               $write ("Bitwise AND generate if MASK [%1d] = %d\n", g, MASK[g]);
 `endif
-	    end
-	 end
+            end
+         end
       end
    endgenerate
 
@@ -94,12 +94,12 @@ module test_gen
    generate
       for (g = 0; g < `MAX_SIZE; g = g + 1) begin
          if (!((g >= SIZE) | ~MASK[g])) begin
-	    always @(posedge clk) begin
+            always @(posedge clk) begin
 `ifdef TEST_VERBOSE
-	       $write ("Bitwise OR generate if MASK [%1d] = %d\n", g, MASK[g]);
+               $write ("Bitwise OR generate if MASK [%1d] = %d\n", g, MASK[g]);
 `endif
-	    end
-	 end
+            end
+         end
       end
    endgenerate
 
diff --git a/test_regress/t/t_gen_upscope.v b/test_regress/t/t_gen_upscope.v
index feebb2c61..474658bdb 100644
--- a/test_regress/t/t_gen_upscope.v
+++ b/test_regress/t/t_gen_upscope.v
@@ -35,7 +35,7 @@ module t (/*AUTOARG*/
    clk
    );
    input clk;
-   integer 	cyc=0;
+   integer      cyc=0;
 
    tag tag ();
    b b ();
@@ -48,8 +48,8 @@ module t (/*AUTOARG*/
    always @(posedge clk) begin
       cyc <= cyc + 1;
       if (cyc==99) begin
-	 $write("*-* All Finished *-*\n");
-	 $finish;
+         $write("*-* All Finished *-*\n");
+         $finish;
       end
    end
 endmodule
@@ -58,8 +58,8 @@ module b ();
    genvar g;
    generate
       for (g=0; g<2; g++) begin : gen
-	 tag tag ();
-	 c c ();
+         tag tag ();
+         c c ();
       end
    endgenerate
    always @ (t.cyc) begin
diff --git a/test_regress/t/t_initial_dlyass.v b/test_regress/t/t_initial_dlyass.v
index 629599a4b..820ec5c5b 100644
--- a/test_regress/t/t_initial_dlyass.v
+++ b/test_regress/t/t_initial_dlyass.v
@@ -21,10 +21,10 @@ module t (/*AUTOARG*/
    always @ (posedge clk) begin
       cyc <= cyc + 1;
       if (cyc==99) begin
-	 if (a != 22) $stop;
-	 if (b != 33) $stop;
-	 $write("*-* All Finished *-*\n");
-	 $finish;
+         if (a != 22) $stop;
+         if (b != 33) $stop;
+         $write("*-* All Finished *-*\n");
+         $finish;
       end
    end
 
diff --git a/test_regress/t/t_inst_overwide.v b/test_regress/t/t_inst_overwide.v
index 85d4b8b32..339cfc024 100644
--- a/test_regress/t/t_inst_overwide.v
+++ b/test_regress/t/t_inst_overwide.v
@@ -18,14 +18,14 @@ module t (/*AUTOARG*/
    output [72:0] outd_w73;
 
    sub sub (
-	    // Outputs
-	    .outy_w92	(outc_w30),	// .large => (small)
-	    .outz_w22	(outd_w73),	// .small => (large)
-	    // Inputs
-	    .clk	(clk),
-	    .inw_w31	(ina_w1),	// .large <= (small)
-	    .inx_w11	(inb_w61)	// .small <= (large)
-	    );
+            // Outputs
+            .outy_w92   (outc_w30),     // .large => (small)
+            .outz_w22   (outd_w73),     // .small => (large)
+            // Inputs
+            .clk        (clk),
+            .inw_w31    (ina_w1),       // .large <= (small)
+            .inx_w11    (inb_w61)       // .small <= (large)
+            );
 
 endmodule
 
@@ -36,9 +36,9 @@ module sub (/*AUTOARG*/
    clk, inw_w31, inx_w11
    );
 
-   input 	clk;
-   input [30:0]	inw_w31;
-   input [10:0]	inx_w11;
+   input        clk;
+   input [30:0] inw_w31;
+   input [10:0] inx_w11;
    output reg [91:0] outy_w92  /*verilator public*/;
    output reg [21:0] outz_w22  /*verilator public*/;
 
diff --git a/test_regress/t/t_interface_missing_bad.v b/test_regress/t/t_interface_missing_bad.v
index 410c3c004..9e7209976 100644
--- a/test_regress/t/t_interface_missing_bad.v
+++ b/test_regress/t/t_interface_missing_bad.v
@@ -21,8 +21,8 @@ module t (/*AUTOARG*/);
    foo_mod
      foo_mod
        (
-	.foo (the_foo)
-	);
+        .foo (the_foo)
+        );
 
    initial begin
       $write("*-* All Finished *-*\n");
diff --git a/test_regress/t/t_interface_typo_bad.v b/test_regress/t/t_interface_typo_bad.v
index b2b1e70da..d91f3393b 100644
--- a/test_regress/t/t_interface_typo_bad.v
+++ b/test_regress/t/t_interface_typo_bad.v
@@ -23,7 +23,7 @@ module t (/*AUTOARG*/);
    submod
      submod_inst
        (
-	.foo (the_foo)
-	);
+        .foo (the_foo)
+        );
 
 endmodule
diff --git a/test_regress/t/t_lint_always_comb_bad.v b/test_regress/t/t_lint_always_comb_bad.v
index 6287ddb44..789eaef96 100644
--- a/test_regress/t/t_lint_always_comb_bad.v
+++ b/test_regress/t/t_lint_always_comb_bad.v
@@ -11,7 +11,7 @@ module t (/*AUTOARG*/
    );
    input clk;
    output logic mid;
-   input 	i3;
+   input        i3;
    output logic o3;
 
    wire [15:0] temp1;
@@ -25,19 +25,19 @@ module t (/*AUTOARG*/
 
    always_comb begin
       if (mid)
-	temp1 = 'h0;
+        temp1 = 'h0;
       else
-	temp1 = (temp1_d1r - 'h1);
+        temp1 = (temp1_d1r - 'h1);
       mid = (temp1_d1r == 'h0);  // BAD
    end
 
    always_comb begin
       o3 = 'h0;
       case (i3)
-	1'b1: begin
-	   o3 = i3;
-	end
-	default: ;
+        1'b1: begin
+           o3 = i3;
+        end
+        default: ;
       endcase
    end
 
diff --git a/test_regress/t/t_lint_blksync_bad.v b/test_regress/t/t_lint_blksync_bad.v
index 159b7911e..ff0f9334e 100644
--- a/test_regress/t/t_lint_blksync_bad.v
+++ b/test_regress/t/t_lint_blksync_bad.v
@@ -11,13 +11,13 @@ module t (/*AUTOARG*/
 
    integer i;
 
-   reg 	 sync_blk;
-   reg 	 sync_blk2;
-   reg 	 sync_nblk;
+   reg   sync_blk;
+   reg   sync_blk2;
+   reg   sync_nblk;
    reg   sync2_ok;
    reg   sync3_ok;
-   reg 	 combo_blk;
-   reg 	 combo_nblk;
+   reg   combo_blk;
+   reg   combo_nblk;
 
    always @(posedge clk) begin
       sync_blk = 1'b1;
@@ -32,7 +32,7 @@ module t (/*AUTOARG*/
 
    always @(posedge clk) begin
       for (int i=0; i<20; i++) begin
-	 sync2_ok <= 1'b1;
+         sync2_ok <= 1'b1;
       end
    end
 
diff --git a/test_regress/t/t_lint_pindup_bad.v b/test_regress/t/t_lint_pindup_bad.v
index 6a8779be1..e521e9037 100644
--- a/test_regress/t/t_lint_pindup_bad.v
+++ b/test_regress/t/t_lint_pindup_bad.v
@@ -13,9 +13,9 @@ module t
    sub
      #(, .P(2), .P(3))
    sub (.o(o),
-	.i(i),
-	.i(i2),
-	);
+        .i(i),
+        .i(i2),
+        );
 
 endmodule
 
diff --git a/test_regress/t/t_lint_setout_bad.v b/test_regress/t/t_lint_setout_bad.v
index 027c76b42..0b8b01f75 100644
--- a/test_regress/t/t_lint_setout_bad.v
+++ b/test_regress/t/t_lint_setout_bad.v
@@ -19,16 +19,16 @@ endmodule
 
 module sub
   (
-   input wire	clk, reset_l,
-   output reg	cpu_if_timeout
+   input wire   clk, reset_l,
+   output reg   cpu_if_timeout
    );
 
    always @(posedge clk) begin
       if (!reset_l) begin
-	 cpu_if_timeout <= 1'b0;
+         cpu_if_timeout <= 1'b0;
       end
       else begin
-	 cpu_if_timeout <= 1'b0;
+         cpu_if_timeout <= 1'b0;
       end
    end
 endmodule
diff --git a/test_regress/t/t_lint_syncasyncnet_bad.v b/test_regress/t/t_lint_syncasyncnet_bad.v
index f4ca14e93..42aedf2fb 100644
--- a/test_regress/t/t_lint_syncasyncnet_bad.v
+++ b/test_regress/t/t_lint_syncasyncnet_bad.v
@@ -45,12 +45,12 @@ module sub1 (/*AUTOARG*/
 
    always @(posedge clk) begin
       if (~rst_sync_l) begin
-	 /*AUTORESET*/
+         /*AUTORESET*/
 	 // Beginning of autoreset for uninitialized flops
 	 q1 <= 1'h0;
 	 // End of automatics
       end else begin
-	 q1 <= d;
+         q1 <= d;
       end
    end
 
@@ -71,18 +71,18 @@ module sub2 (/*AUTOARG*/
    //input rst_sync_l;
    input rst_async_l;
    input d;
-   reg 	 q1;
-   reg 	 q2;
-   reg 	 q3;
+   reg   q1;
+   reg   q2;
+   reg   q3;
 
    always @(posedge clk or negedge rst_async_l) begin
       if (~rst_async_l) begin
-	 /*AUTORESET*/
+         /*AUTORESET*/
 	 // Beginning of autoreset for uninitialized flops
 	 q1 <= 1'h0;
 	 // End of automatics
       end else begin
-	 q1 <= d;
+         q1 <= d;
       end
    end
 
diff --git a/test_regress/t/t_lint_width_bad.v b/test_regress/t/t_lint_width_bad.v
index 8327029e0..3496242ec 100644
--- a/test_regress/t/t_lint_width_bad.v
+++ b/test_regress/t/t_lint_width_bad.v
@@ -13,22 +13,22 @@ module t ();
    p #(.WIDTH(5)) p5 (.in(5'd0));
 
    //====
-   localparam [3:0]	XS = 'hx;  // User presumably intended to use 'x
+   localparam [3:0]     XS = 'hx;  // User presumably intended to use 'x
 
    //====
    wire [4:0] c = 1'b1 << 2;  // No width warning, as is common syntax
    wire [4:0] d = (1'b1 << 2) + 5'b1;  // Has warning as not obvious what expression width is
 
    //====
-   localparam		WIDTH = 6;
-   wire 		one_bit;
-   wire	[2:0]		shifter = 1;
-   wire [WIDTH-1:0] 	masked = (({{(WIDTH){1'b0}}, one_bit}) << shifter);
+   localparam           WIDTH = 6;
+   wire                 one_bit;
+   wire [2:0]           shifter = 1;
+   wire [WIDTH-1:0]     masked = (({{(WIDTH){1'b0}}, one_bit}) << shifter);
 
    //====
    // We presently warn here, in theory we could detect if the number of one bit additions could overflow the LHS
-   wire 		one = 1;
-   wire [2:0] 		cnt  = (one + one + one + one);
+   wire                 one = 1;
+   wire [2:0]           cnt  = (one + one + one + one);
 
 endmodule
 
diff --git a/test_regress/t/t_mem_multi_ref_bad.v b/test_regress/t/t_mem_multi_ref_bad.v
index 9533f97c5..099640e3f 100644
--- a/test_regress/t/t_mem_multi_ref_bad.v
+++ b/test_regress/t/t_mem_multi_ref_bad.v
@@ -8,18 +8,18 @@ module t (/*AUTOARG*/);
    reg [1:0] dim0;
    reg [1:0] dim1 [1:0];
    reg [1:0] dim2 [1:0][1:0];
-   reg	     dim0nv[1:0];
+   reg       dim0nv[1:0];
 
    initial begin
-      dimn[1:0] = 0;		// Bad: Not ranged
-      dim0[1][1] = 0;		// Bad: Not arrayed
-      dim1[1][1][1] = 0;	// Bad: Not arrayed to right depth
-      dim2[1][1][1] = 0;	// OK
-      dim2[0 +: 1][1] = 0;	// Bad: Range on non-bits
-      dim2[1 : 0][1] = 0;	// Bad: Range on non-bits
-      dim2[1][1:0] = 0;		// Bad: Bitsel too soon
-      dim0nv[1:0] = 0;		// Bad: Not vectored
-      dim0nv[1][1] = 0;		// Bad: Not arrayed to right depth
+      dimn[1:0] = 0;            // Bad: Not ranged
+      dim0[1][1] = 0;           // Bad: Not arrayed
+      dim1[1][1][1] = 0;        // Bad: Not arrayed to right depth
+      dim2[1][1][1] = 0;        // OK
+      dim2[0 +: 1][1] = 0;      // Bad: Range on non-bits
+      dim2[1 : 0][1] = 0;       // Bad: Range on non-bits
+      dim2[1][1:0] = 0;         // Bad: Bitsel too soon
+      dim0nv[1:0] = 0;          // Bad: Not vectored
+      dim0nv[1][1] = 0;         // Bad: Not arrayed to right depth
    end
 
 endmodule
diff --git a/test_regress/t/t_order_clkinst.v b/test_regress/t/t_order_clkinst.v
index 92f873c9a..a1ed5559a 100644
--- a/test_regress/t/t_order_clkinst.v
+++ b/test_regress/t/t_order_clkinst.v
@@ -14,7 +14,7 @@ module t (/*AUTOARG*/
    // verilator lint_off UNOPTFLAT
    // verilator lint_off BLKANDNBLK
 
-   reg 	       c1_start; initial c1_start = 0;
+   reg         c1_start; initial c1_start = 0;
    wire [31:0] c1_count;
    comb_loop c1 (.count(c1_count), .start(c1_start));
 
@@ -31,29 +31,29 @@ module t (/*AUTOARG*/
       //$write("[%0t] %x  counts %x %x %x\n",$time,cyc,c1_count,s2_count,c3_count);
       cyc <= cyc + 8'd1;
       case (cyc)
-	8'd00: begin
-	   c1_start <= 1'b0;
-	end
-	8'd01: begin
-	   c1_start <= 1'b1;
-	end
-	default: ;
+        8'd00: begin
+           c1_start <= 1'b0;
+        end
+        8'd01: begin
+           c1_start <= 1'b1;
+        end
+        default: ;
       endcase
       case (cyc)
-	8'd02: begin
+        8'd02: begin
            // On Verilator, we expect these comparisons to match exactly,
            // confirming that our settle loop repeated the exact number of
            // iterations we expect. No '$stop' should be called here, and we
            // should reach the normal '$finish' below on the next cycle.
-	   if (c1_count!=32'h3) $stop;
-	   if (s2_count!=32'h3) $stop;
+           if (c1_count!=32'h3) $stop;
+           if (s2_count!=32'h3) $stop;
            if (c3_count!=32'h5) $stop;
-	end
-	8'd03: begin
-	   $write("*-* All Finished *-*\n");
-	   $finish;
-	end
-	default: ;
+        end
+        8'd03: begin
+           $write("*-* All Finished *-*\n");
+           $finish;
+        end
+        default: ;
       endcase
    end
 endmodule
@@ -67,7 +67,7 @@ module comb_loop (/*AUTOARG*/
    input start;
    output reg [31:0] count; initial count = 0;
 
-   reg [31:0] 	 runnerm1, runner; initial runner = 0;
+   reg [31:0]    runnerm1, runner; initial runner = 0;
 
    always @ (posedge start) begin
       runner = 3;
@@ -79,9 +79,9 @@ module comb_loop (/*AUTOARG*/
 
    always @ (/*AS*/runnerm1) begin
       if (runner > 0) begin
-	 count = count + 1;
-	 runner = runnerm1;
-	 $write ("%m count=%d  runner =%x\n",count, runnerm1);
+         count = count + 1;
+         runner = runnerm1;
+         $write ("%m count=%d  runner =%x\n",count, runnerm1);
       end
    end
 
@@ -96,7 +96,7 @@ module seq_loop (/*AUTOARG*/
    input start;
    output reg [31:0] count; initial count = 0;
 
-   reg [31:0] 	 runnerm1, runner; initial runner = 0;
+   reg [31:0]    runnerm1, runner; initial runner = 0;
 
    always @ (posedge start) begin
       runner <= 3;
@@ -108,9 +108,9 @@ module seq_loop (/*AUTOARG*/
 
    always @ (/*AS*/runnerm1) begin
       if (runner > 0) begin
-	 count = count + 1;
-	 runner <= runnerm1;
-	 $write ("%m count=%d  runner<=%x\n",count, runnerm1);
+         count = count + 1;
+         runner <= runnerm1;
+         $write ("%m count=%d  runner<=%x\n",count, runnerm1);
       end
    end
 
diff --git a/test_regress/t/t_order_loop_bad.v b/test_regress/t/t_order_loop_bad.v
index 231c2d0cd..6b6b51a41 100644
--- a/test_regress/t/t_order_loop_bad.v
+++ b/test_regress/t/t_order_loop_bad.v
@@ -15,7 +15,7 @@ module t (/*AUTOARG*/
    );
    input clk;
 
-   reg 	 ready;
+   reg   ready;
 
    initial begin
       ready = 1'b0;
@@ -23,8 +23,8 @@ module t (/*AUTOARG*/
 
    always @(posedge ready) begin
       if ((ready === 1'b1)) begin
-	 $write("*-* All Finished *-*\n");
-	 $finish;
+         $write("*-* All Finished *-*\n");
+         $finish;
       end
    end
 
diff --git a/test_regress/t/t_param_concat.v b/test_regress/t/t_param_concat.v
index b4300142a..11fde4e7a 100644
--- a/test_regress/t/t_param_concat.v
+++ b/test_regress/t/t_param_concat.v
@@ -9,18 +9,18 @@ module t (/*AUTOARG*/
    );
    input clk;
 
-   parameter	UNSIZED = 10;
+   parameter    UNSIZED = 10;
 
    integer cyc=1;
    always @ (posedge clk) begin
       cyc <= cyc + 1;
       if (cyc==1) begin
-	 if ({UNSIZED,UNSIZED+1} != {32'd10, 32'd11}) $stop;
-	 if ({2{UNSIZED}} != {32'd10, 32'd10}) $stop;
+         if ({UNSIZED,UNSIZED+1} != {32'd10, 32'd11}) $stop;
+         if ({2{UNSIZED}} != {32'd10, 32'd10}) $stop;
       end
       if (cyc==9) begin
-	 $write("*-* All Finished *-*\n");
-	 $finish;
+         $write("*-* All Finished *-*\n");
+         $finish;
       end
    end
 
diff --git a/test_regress/t/t_select_bad_range2.v b/test_regress/t/t_select_bad_range2.v
index 73486f83c..3717cb792 100644
--- a/test_regress/t/t_select_bad_range2.v
+++ b/test_regress/t/t_select_bad_range2.v
@@ -31,8 +31,8 @@ module t (/*AUTOARG*/
       $write("[%0t] in=%d out32=%d out10=%d\n",$time, in, out32, out10);
 `endif
       if (in==3) begin
-	 $write("*-* All Finished *-*\n");
-	 $finish;
+         $write("*-* All Finished *-*\n");
+         $finish;
       end
    end
 endmodule
diff --git a/test_regress/t/t_struct_init.v b/test_regress/t/t_struct_init.v
index efcaaffbb..914ac28cd 100644
--- a/test_regress/t/t_struct_init.v
+++ b/test_regress/t/t_struct_init.v
@@ -6,37 +6,37 @@
 module t;
 
    //Several simulators don't support this.
-   //typedef struct pack2;	// Forward declaration
+   //typedef struct pack2;      // Forward declaration
 
    typedef struct packed { // [3:0]
-      bit	b3;
-      bit	b2;
-      bit	b1;
-      bit	b0;
+      bit       b3;
+      bit       b2;
+      bit       b1;
+      bit       b0;
    } b4_t;
 
    typedef struct packed { // [3:0]
-      b4_t	x1;
-      b4_t	x0;
+      b4_t      x1;
+      b4_t      x0;
    } b4x2_t;
 
    typedef union packed { // [3:0]
-      bit [3:0]	quad0;
-      b4_t	quad1;
+      bit [3:0] quad0;
+      b4_t      quad1;
    } q4_t;
 
    typedef struct packed { // [5:0]
-      bit	msb;
-      q4_t	four;
-      bit	lsb;
+      bit       msb;
+      q4_t      four;
+      bit       lsb;
    } pack2_t;
 
    typedef union packed { // [5:0]
-      pack2_t	pack2;
+      pack2_t   pack2;
       bit [6:1] pvec;
       // Vector not allowed in packed structure, per spec:
-      //      bit	vec[6];
-      //      bit 	vec2d[2][3];
+      //      bit       vec[6];
+      //      bit       vec2d[2][3];
    } pack3_t;
 
    const b4_t b4_const_a = '{1'b1, 1'b0, 1'b0, 1'b1};
@@ -81,32 +81,32 @@ module t;
       //
       // Initialization
       begin
-	 b4_t q = '{1'b1, 1'b1, 1'b0, 1'b0};
-	 if (q != 4'b1100) $stop;
+         b4_t q = '{1'b1, 1'b1, 1'b0, 1'b0};
+         if (q != 4'b1100) $stop;
       end
       begin
-	 b4_t q = '{3{1'b1}, 1'b0};
-	 if (q != 4'b1110) $stop;
+         b4_t q = '{3{1'b1}, 1'b0};
+         if (q != 4'b1110) $stop;
       end
       begin
-	 b4_t q = '{4{1'b1}};	// Repeats the {}
-	 if (q != 4'b1111) $stop;
+         b4_t q = '{4{1'b1}};   // Repeats the {}
+         if (q != 4'b1111) $stop;
       end
       begin
-	 b4x2_t m = '{4'b1001, '{1'b1, 1'b0, 1'b1, 1'b1}};
-	 if (m != 8'b10011011) $stop;
+         b4x2_t m = '{4'b1001, '{1'b1, 1'b0, 1'b1, 1'b1}};
+         if (m != 8'b10011011) $stop;
       end
       begin
-	 b4_t q = '{default:1'b1};
-	 if (q != 4'b1111) $stop;
+         b4_t q = '{default:1'b1};
+         if (q != 4'b1111) $stop;
       end
       begin
-	 b4_t q = '{b0:1'b1, b2:1'b1, b3:1'b1, b1:1'b0};
-	 if (q != 4'b1101) $stop;
+         b4_t q = '{b0:1'b1, b2:1'b1, b3:1'b1, b1:1'b0};
+         if (q != 4'b1101) $stop;
       end
       begin
-	 b4_t q = '{b2:1'b0, default:1'b1};
-	 if (q != 4'b1011) $stop;
+         b4_t q = '{b2:1'b0, default:1'b1};
+         if (q != 4'b1011) $stop;
       end
 
       if (b4_const_a != 4'b1001) $stop;
diff --git a/test_regress/t/t_udp.v b/test_regress/t/t_udp.v
index f39f35209..e946fd876 100644
--- a/test_regress/t/t_udp.v
+++ b/test_regress/t/t_udp.v
@@ -9,36 +9,33 @@ module t (/*AUTOARG*/
    );
    input clk;
 
-   integer 	cyc=0;
-   reg [63:0] 	crc;
-   reg [63:0] 	sum;
+   integer      cyc=0;
+   reg [63:0]   crc;
+   reg [63:0]   sum;
 
    // Take CRC data and apply to testblock inputs
    wire [31:0]  in = crc[31:0];
 
    /*AUTOWIRE*/
-   // Beginning of automatic wires (for undeclared instantiated-module outputs)
-   wire [31:0] 		out;			// From test of Test.v
-   // End of automatics
 
    // Async clears must not race with clocks if we want repeatable results
-   reg 		set_l = in[20];
-   reg 		clr_l = in[21];
+   reg          set_l = in[20];
+   reg          clr_l = in[21];
    always @ (negedge clk) begin
       set_l <= in[20];
       clr_l <= in[21];
    end
 
    //====== Mux
-   wire [1:0] 		qm;
+   wire [1:0]           qm;
    //       delay      z      a      b      sel
    udp_mux2 #(0.1) m0 (qm[0], in[0], in[2], in[4]);
    udp_mux2 #0.1   m1 (qm[1], in[1], in[3], in[4]);
 
 `define verilatorxx
 `ifdef verilatorxx
-   reg [1:0] 		ql;
-   reg [1:0] 		qd;
+   reg [1:0]            ql;
+   reg [1:0]            qd;
 
    // No sequential tables, yet
 //   always @* begin
@@ -51,13 +48,13 @@ module t (/*AUTOARG*/
    end
 `else
    //====== Latch
-//   wire [1:0] 		ql;
+//   wire [1:0]                 ql;
 //   //            q      clk    d
 //   udp_latch l0 (ql[0], !in[8], in[12]);
 //   udp_latch l1 (ql[1], !in[8], in[13]);
 
    //====== DFF
-   wire [1:0] 		qd;
+   wire [1:0]           qd;
    //always @* $display("UL q=%b c=%b d=%b", ql[1:0], in[8], in[13:12]);
    //            q      clk     d      set_l  clr_l
    udp_dff   d0 (qd[0], in[8], in[16], set_l, clr_l);
@@ -77,24 +74,24 @@ module t (/*AUTOARG*/
       crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
       sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
       if (cyc==0) begin
-	 // Setup
-	 crc <= 64'h5aef0c8d_d70a4497;
-	 sum <= 64'h0;
+         // Setup
+         crc <= 64'h5aef0c8d_d70a4497;
+         sum <= 64'h0;
       end
       else if (cyc<10) begin
-	 sum <= 64'h0;
+         sum <= 64'h0;
       end
       else if (cyc<90) begin
       end
       else if (cyc==99) begin
-	 $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
-	 if (crc !== 64'hc77bb9b3784ea091) $stop;
-	 // What checksum will we end up with (above print should match)
-	 // Note not all simulators agree about the latch result.  Maybe have a race?
+         $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
+         if (crc !== 64'hc77bb9b3784ea091) $stop;
+         // What checksum will we end up with (above print should match)
+         // Note not all simulators agree about the latch result.  Maybe have a race?
 `define EXPECTED_SUM 64'hb73acf228acaeaa3
-	 if (sum !== `EXPECTED_SUM) $stop;
-	 $write("*-* All Finished *-*\n");
-	 $finish;
+         if (sum !== `EXPECTED_SUM) $stop;
+         $write("*-* All Finished *-*\n");
+         $finish;
       end
    end
 
diff --git a/test_regress/t/t_udp_bad.out b/test_regress/t/t_udp_bad.out
index b7c074535..91d6ab5b9 100644
--- a/test_regress/t/t_udp_bad.out
+++ b/test_regress/t/t_udp_bad.out
@@ -1,2 +1,2 @@
-%Error: t/t_udp.v:106: Unsupported: Verilog 1995 UDP Tables.  Use --bbox-unsup to ignore tables.
+%Error: t/t_udp.v:103: Unsupported: Verilog 1995 UDP Tables.  Use --bbox-unsup to ignore tables.
 %Error: Exiting due to
diff --git a/test_regress/t/t_unopt_combo.v b/test_regress/t/t_unopt_combo.v
index f3494ded5..4061814aa 100644
--- a/test_regress/t/t_unopt_combo.v
+++ b/test_regress/t/t_unopt_combo.v
@@ -39,22 +39,22 @@ module t (/*AUTOARG*/
       cyc <= cyc + 1;
       crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
       sum <= {b, d}
-	     ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
+             ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
       if (cyc==0) begin
-	 // Setup
-	 crc <= 64'h5aef0c8d_d70a4497;
+         // Setup
+         crc <= 64'h5aef0c8d_d70a4497;
       end
       else if (cyc<10) begin
-	 sum <= 64'h0;
+         sum <= 64'h0;
       end
       else if (cyc<90) begin
       end
       else if (cyc==99) begin
-	 $write("*-* All Finished *-*\n");
-	 $write("[%0t] cyc==%0d crc=%x %x\n",$time, cyc, crc, sum);
-	 if (crc !== 64'hc77bb9b3784ea091) $stop;
-	 if (sum !== 64'h649ee1713d624dd9) $stop;
-	 $finish;
+         $write("*-* All Finished *-*\n");
+         $write("[%0t] cyc==%0d crc=%x %x\n",$time, cyc, crc, sum);
+         if (crc !== 64'hc77bb9b3784ea091) $stop;
+         if (sum !== 64'h649ee1713d624dd9) $stop;
+         $finish;
       end
    end
 
@@ -80,54 +80,54 @@ module file (/*AUTOARG*/
    always @* begin
       // Note that while c and b depend on crc, b doesn't depend on c.
       casez (crc[3:0])
-	4'b??01: begin
-	   b = {crc[15:0],get_31_16(crc)};
-	   d = c;
-	end
-	4'b??00: begin
-	   b = {crc[15:0],~crc[31:16]};
-	   d = {crc[15:0],~c[31:16]};
-	end
-	default: begin
-	   set_b_d(crc, c);
-	end
+        4'b??01: begin
+           b = {crc[15:0],get_31_16(crc)};
+           d = c;
+        end
+        4'b??00: begin
+           b = {crc[15:0],~crc[31:16]};
+           d = {crc[15:0],~c[31:16]};
+        end
+        default: begin
+           set_b_d(crc, c);
+        end
       endcase
    end
 
-   function [31:16] get_31_16	/* verilator isolate_assignments*/;
-      input [31:0] t_crc	/* verilator isolate_assignments*/;
+   function [31:16] get_31_16   /* verilator isolate_assignments*/;
+      input [31:0] t_crc        /* verilator isolate_assignments*/;
       get_31_16 = t_crc[31:16];
    endfunction
 
    task set_b_d;
 `ifdef ISOLATE
-      input [31:0] t_crc	/* verilator isolate_assignments*/;
-      input [31:0] t_c		/* verilator isolate_assignments*/;
+      input [31:0] t_crc        /* verilator isolate_assignments*/;
+      input [31:0] t_c          /* verilator isolate_assignments*/;
 `else
       input [31:0] t_crc;
       input [31:0] t_c;
 `endif
       begin
-	 b = {t_crc[31:16],~t_crc[23:8]};
-	 d = {t_crc[31:16],  ~t_c[23:8]};
+         b = {t_crc[31:16],~t_crc[23:8]};
+         d = {t_crc[31:16],  ~t_c[23:8]};
       end
    endtask
 
    always @* begin
       // Any complicated equation we can't optimize
       casez (crc[3:0])
-	4'b00??: begin
-	   c = {b[29:0],2'b11};
-	end
-	4'b01??: begin
-	   c = {b[30:1],2'b01};
-	end
-	4'b10??: begin
-	   c = {b[31:2],2'b10};
-	end
-	4'b11??: begin
-	   c = {b[31:2],2'b00};
-	end
+        4'b00??: begin
+           c = {b[29:0],2'b11};
+        end
+        4'b01??: begin
+           c = {b[30:1],2'b01};
+        end
+        4'b10??: begin
+           c = {b[31:2],2'b10};
+        end
+        4'b11??: begin
+           c = {b[31:2],2'b00};
+        end
       endcase
    end
 
diff --git a/test_regress/t/t_var_nonamebegin.v b/test_regress/t/t_var_nonamebegin.v
index 4adb27c65..03a25363c 100644
--- a/test_regress/t/t_var_nonamebegin.v
+++ b/test_regress/t/t_var_nonamebegin.v
@@ -3,59 +3,59 @@ module t (/*AUTOARG*/
    clk, reset_l
    );
 
-   input	clk;
-   input	reset_l;
+   input        clk;
+   input        reset_l;
 
-   reg 		inmod;
+   reg          inmod;
 
    generate
       if (1) begin
-	 // Traces as genblk1.ingen
-	 integer ingen;
-	 initial $display("ingen: {mod}.genblk1 %m");
+         // Traces as genblk1.ingen
+         integer ingen;
+         initial $display("ingen: {mod}.genblk1 %m");
       end
    endgenerate
 
-   integer 	 rawmod;
+   integer       rawmod;
 
    initial begin
       begin
-	 integer upa;
-	 begin : d3nameda
-	    // %m='.d3nameda'  var=_unnamed#.d3nameda.b1
-	    integer d3a;
-	    $display("d3a: {mod}.d3nameda %m");
-	 end
+         integer upa;
+         begin : d3nameda
+            // %m='.d3nameda'  var=_unnamed#.d3nameda.b1
+            integer d3a;
+            $display("d3a: {mod}.d3nameda %m");
+         end
       end
    end
    initial begin
       integer b2;
       $display("b2: {mod} %m");
       begin : b3named
-	 integer b3n;
-	 $display("b3n: {mod}.b3named: %m");
+         integer b3n;
+         $display("b3n: {mod}.b3named: %m");
       end
       if (1) begin
-	 integer b3;
-	 $display("b3: {mod} %m");
-	 if (1) begin
-	    begin
-	       begin
-		  begin
-		     integer b4;
-		     $display("b4: {mod} %m");
-		  end
-	       end
-	    end
-	 end
-	 else begin
-	    integer b4;
-	    $display("bb %m");
-	 end
+         integer b3;
+         $display("b3: {mod} %m");
+         if (1) begin
+            begin
+               begin
+                  begin
+                     integer b4;
+                     $display("b4: {mod} %m");
+                  end
+               end
+            end
+         end
+         else begin
+            integer b4;
+            $display("bb %m");
+         end
       end
       else begin
-	 integer b4;
-	 $display("b4 %m");
+         integer b4;
+         $display("b4 %m");
       end
       tsk;
       $write("*-* All Finished *-*\n");
@@ -66,8 +66,8 @@ module t (/*AUTOARG*/
       integer t1;
       $display("t1 {mod}.tsk %m");
       begin
-	 integer t2;
-	 $display("t2 {mod}.tsk %m");
+         integer t2;
+         $display("t2 {mod}.tsk %m");
       end
    endtask
 
diff --git a/test_regress/t/t_var_rsvd_port.v b/test_regress/t/t_var_rsvd_port.v
index 63029b5f0..615bba58a 100644
--- a/test_regress/t/t_var_rsvd_port.v
+++ b/test_regress/t/t_var_rsvd_port.v
@@ -8,10 +8,10 @@ module t (/*AUTOARG*/
    bool
    );
 
-   input bool;	// BAD
+   input bool;  // BAD
 
-   reg  vector;	// OK, as not public
-   reg  switch /*verilator public*/;	// Bad
+   reg  vector; // OK, as not public
+   reg  switch /*verilator public*/;    // Bad
 
    initial begin
       $write("*-* All Finished *-*\n");
diff --git a/test_regress/t/t_var_types_bad.v b/test_regress/t/t_var_types_bad.v
index 53c610728..e67cd7655 100644
--- a/test_regress/t/t_var_types_bad.v
+++ b/test_regress/t/t_var_types_bad.v
@@ -6,55 +6,55 @@
 module t (/*AUTOARG*/);
 
    // IEEE: integer_atom_type
-   byte		d_byte;
-   shortint	d_shortint;
-   int		d_int;
-   longint	d_longint;
-   integer	d_integer;
-   time		d_time;
-   chandle	d_chandle;
+   byte         d_byte;
+   shortint     d_shortint;
+   int          d_int;
+   longint      d_longint;
+   integer      d_integer;
+   time         d_time;
+   chandle      d_chandle;
 
    // IEEE: integer_atom_type
-   bit		d_bit;
-   logic	d_logic;
-   reg		d_reg;
+   bit          d_bit;
+   logic        d_logic;
+   reg          d_reg;
 
-   bit [0:0]	d_bit1;
-   logic [0:0]	d_logic1;
-   reg [0:0]	d_reg1;
+   bit [0:0]    d_bit1;
+   logic [0:0]  d_logic1;
+   reg [0:0]    d_reg1;
 
-   bit		d_bitz;
-   logic	d_logicz;
-   reg		d_regz;
+   bit          d_bitz;
+   logic        d_logicz;
+   reg          d_regz;
 
    // IEEE: non_integer_type
-   //UNSUP shortreal	d_shortreal;
-   real		d_real;
-   realtime	d_realtime;
+   //UNSUP shortreal    d_shortreal;
+   real         d_real;
+   realtime     d_realtime;
 
    initial begin
       // below errors might cause spurious warnings
       // verilator lint_off WIDTH
-      d_bitz[0] = 1'b1;		// Illegal range
-      d_logicz[0] = 1'b1;	// Illegal range
-      d_regz[0] = 1'b1;		// Illegal range
+      d_bitz[0] = 1'b1;         // Illegal range
+      d_logicz[0] = 1'b1;       // Illegal range
+      d_regz[0] = 1'b1;         // Illegal range
 
 `ifndef VERILATOR //UNSUPPORTED, it's just a 64 bit int right now
-      d_chandle[0] = 1'b1;	// Illegal
+      d_chandle[0] = 1'b1;      // Illegal
 `endif
-      d_real[0] = 1'b1;		// Illegal
-      d_realtime[0] = 1'b1;	// Illegal
+      d_real[0] = 1'b1;         // Illegal
+      d_realtime[0] = 1'b1;     // Illegal
       // verilator lint_on WIDTH
 
-      d_byte[0] = 1'b1;		// OK
-      d_shortint[0] = 1'b1;	// OK
-      d_int[0] = 1'b1;		// OK
-      d_longint[0] = 1'b1;	// OK
-      d_integer[0] = 1'b1;	// OK
-      d_time[0] = 1'b1;		// OK
+      d_byte[0] = 1'b1;         // OK
+      d_shortint[0] = 1'b1;     // OK
+      d_int[0] = 1'b1;          // OK
+      d_longint[0] = 1'b1;      // OK
+      d_integer[0] = 1'b1;      // OK
+      d_time[0] = 1'b1;         // OK
 
-      d_bit1[0] = 1'b1;		// OK
-      d_logic1[0] = 1'b1;	// OK
-      d_reg1[0] = 1'b1;		// OK
+      d_bit1[0] = 1'b1;         // OK
+      d_logic1[0] = 1'b1;       // OK
+      d_reg1[0] = 1'b1;         // OK
    end
 endmodule