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More bison cleanup; no functional change
git-svn-id: file://localhost/svn/verilator/trunk/verilator@921 77ca24e4-aefa-0310-84f0-b9a241c72d87
This commit is contained in:
Wilson Snyder
parent
a77e331e89
commit
b3dd18b215
2
TODO
2
TODO
@ -26,11 +26,11 @@ Features:
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Points should be per-scope like everything else rather then per-module
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Expression coverage (see notes)
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More Verilog 2001 Support
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C-style function and task arguments. [Wim Michiels]
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(* *) Attributes (just ignore -- preprocessor?)
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Real numbers (NEVER)
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Recursive functions (NEVER)
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Verilog configuration files (NEVER)
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DPI to define C/C++ calls from Verilog
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Long-term Features
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Assertions
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67
nodist/bisonreader
Executable file
67
nodist/bisonreader
Executable file
@ -0,0 +1,67 @@
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#!/usr/bin/perl -w
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#$Id$
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######################################################################
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#
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# Copyright 2007-2007 by Wilson Snyder.
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#
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of either the GNU General Public License or the
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# Perl Artistic License.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the Perl Artistic License
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# along with this module; see the file COPYING. If not, see
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# www.cpan.org
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#
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######################################################################
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# DESCRIPTION: Debugging of bison output
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use strict;
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my $Debug;
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my %declared;
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my %used;
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my $body = 0;
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my $rule = "";
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my $lineno = 0;
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foreach my $line (<STDIN>) {
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$lineno++;
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chomp $line;
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$line =~ s!//.*$!!g;
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$line =~ s!\s+! !g;
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next if $line eq '';
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if ($line =~ m!^\%\%!) {
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$body++;
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} elsif ($body == 1) {
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$rule .= $line;
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if ($line =~ m!^\s*;\s*$!) {
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#print "Rule: $rule\n";
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($rule =~ /^([a-zA-Z0-9_]+):(.*)$/) or die "%Error: No rule name: $1\n";
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my $rulename = $1; my $preaction = $2;
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$declared{$rulename} = $lineno;
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$preaction =~ s/\{[^\}]*\}/ /g;
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#print "RULEN $rulename PA $preaction\n" if $Debug;
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$rule = '';
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foreach my $ref (split /\s+/, $preaction) {
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next if $ref !~ /^[a-zA-Z]/;
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next if $ref eq $rulename;
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if (!$used{$ref} && $declared{$ref}) {
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print " %Warning: $lineno: $ref used by $rulename after declaration\n";
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}
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$used{$ref} = $lineno;
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print " ref $ref\n" if $Debug;
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}
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}
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}
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}
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# Local Variables:
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# compile-command: "./bisonreader < verilog.y"
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# End:
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293
src/verilog.y
293
src/verilog.y
@ -283,21 +283,21 @@ class AstSenTree;
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// Types are in same order as declarations.
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// Naming:
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// Trailing E indicates this type may have empty match
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%type<modulep> mheader
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%type<nodep> modportsE portList port
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%type<nodep> v2kPortList v2kPortSig
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%type<nodep> v2kPort ioDecl varDecl
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%type<modulep> modHdr
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%type<nodep> modPortsE portList port
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%type<nodep> portV2kList portV2kSig
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%type<nodep> portV2kDecl ioDecl varDecl
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%type<nodep> modParDecl modParList modParE
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%type<nodep> modItem modItemList modItemListE modOrGenItem
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%type<nodep> genItem genItemList genItemBegin genItemBlock genTopBlock genCaseList
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%type<nodep> dterm
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%type<varp> onesig sigId sigIdRange paramId sigList regsig regsigList regSigId
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%type<nodep> dlyTerm
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%type<varp> sigAndAttr sigId sigIdRange sigList regsig regsigList regSigId
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%type<varp> netSig netSigList
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%type<rangep> rangeListE regrangeE anyrange rangeList delayrange portrangeE
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%type<rangep> rangeListE regrangeE anyrange rangeList delayrange portRangeE
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%type<varp> param paramList
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%type<nodep> instnameList
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%type<cellp> instname
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%type<pinp> cellpinList cellpinlist2 cellpinitemE instparamListE
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%type<pinp> cellpinList cellpinItList cellpinitemE instparamListE
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%type<nodep> defpList defpOne
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%type<sentreep> sensitivityE
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%type<senitemp> senList senitem senitemEdge
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@ -306,9 +306,9 @@ class AstSenTree;
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%type<beginp> beginNamed
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%type<casep> caseStmt
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%type<caseitemp> caseList
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%type<nodep> casecondList assignList assignOne
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%type<nodep> caseCondList assignList assignOne
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%type<nodep> constExpr exprNoStr expr exprPsl exprStrText
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%type<nodep> eList cateList cStrList
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%type<nodep> exprList cateList cStrList
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%type<varrefp> varRefBase
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%type<parserefp> varRefMem
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%type<parserefp> varRefDotBit
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@ -321,7 +321,7 @@ class AstSenTree;
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%type<nodep> varDeclList
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%type<funcp> funcDecl
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%type<nodep> funcBody funcVarList funcVar
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%type<rangep> funcRange
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%type<rangep> funcRangeE
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%type<nodep> gateDecl
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%type<nodep> gateBufList gateNotList gateAndList gateNandList
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%type<nodep> gateOrList gateNorList gateXorList gateXnorList
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@ -347,18 +347,21 @@ statePop: { V3Read::statePop(); }
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;
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//**********************************************************************
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// Modules
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// Files
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file: mod
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| file mod
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;
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mod: mheader modParE modportsE ';' modItemListE yENDMODULE
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//**********************************************************************
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// Module headers
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mod: modHdr modParE modPortsE ';' modItemListE yENDMODULE
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{ $1->modTrace(V3Parse::s_trace); // Stash for implicit wires, etc
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if ($2) $1->addStmtp($2); if ($3) $1->addStmtp($3); if ($5) $1->addStmtp($5); }
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;
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mheader: yMODULE { V3Parse::s_trace=v3Global.opt.trace();}
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modHdr: yMODULE { V3Parse::s_trace=v3Global.opt.trace();}
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yaID { $$ = new AstModule($1,*$3); $$->inLibrary(V3Read::inLibrary());
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$$->modTrace(v3Global.opt.trace());
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V3Read::rootp()->addModulep($$); }
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@ -374,28 +377,56 @@ modParList: modParDecl { $$ = $1; }
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| modParList ';' modParDecl { $$ = $1->addNext($3); }
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;
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modportsE: /* empty */ { $$ = NULL; }
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modPortsE: /* empty */ { $$ = NULL; }
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| '(' ')' { $$ = NULL; }
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| '(' {V3Parse::s_pinNum=1;} portList ')' { $$ = $3; }
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| '(' {V3Parse::s_pinNum=1;} v2kPortList ')' { $$ = $3; }
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| '(' {V3Parse::s_pinNum=1;} portV2kList ')' { $$ = $3; }
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;
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portList: port { $$ = $1; }
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| portList ',' port { $$ = $1->addNext($3); }
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;
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port: yaID portrangeE { $$ = new AstPort(CRELINE(),V3Parse::s_pinNum++,*$1); }
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port: yaID portRangeE { $$ = new AstPort(CRELINE(),V3Parse::s_pinNum++,*$1); }
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;
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v2kPortList: v2kPort { $$ = $1; }
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| v2kPortList ',' v2kPort { $$ = $1->addNext($3); }
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portV2kList: portV2kDecl { $$ = $1; }
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| portV2kList ',' portV2kDecl { $$ = $1->addNext($3); }
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;
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v2kPortSig: onesig { $$=$1; $$->addNext(new AstPort(CRELINE(),V3Parse::s_pinNum++, V3Parse::s_varAttrp->name())); }
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portV2kSig: sigAndAttr { $$=$1; $$->addNext(new AstPort(CRELINE(),V3Parse::s_pinNum++, V3Parse::s_varAttrp->name())); }
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;
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//************************************************
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// Variables
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// Variable Declarations
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varDeclList: varDecl { $$ = $1; }
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| varDecl varDeclList { $$ = $1->addNext($2); }
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;
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regsigList: regsig { $$ = $1; }
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| regsigList ',' regsig { $$ = $1;$1->addNext($3); }
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;
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portV2kDecl: varRESET varInput varSignedE v2kNetDeclE regrangeE portV2kSig { $$ = $6; }
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| varRESET varInout varSignedE v2kNetDeclE regrangeE portV2kSig { $$ = $6; }
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| varRESET varOutput varSignedE v2kVarDecl regrangeE portV2kSig { $$ = $6; }
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;
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ioDecl: varRESET varInput varSignedE v2kNetDeclE regrangeE sigList ';' { $$ = $6; }
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| varRESET varInout varSignedE v2kNetDeclE regrangeE sigList ';' { $$ = $6; }
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| varRESET varOutput varSignedE v2kVarDecl regrangeE sigList ';' { $$ = $6; }
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;
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varDecl: varRESET varReg varSignedE regrangeE regsigList ';' { $$ = $5; }
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| varRESET varGParam varSignedE regrangeE paramList ';' { $$ = $5; }
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| varRESET varLParam varSignedE regrangeE paramList ';' { $$ = $5; }
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| varRESET varNet varSignedE delayrange netSigList ';' { $$ = $5; }
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| varRESET varGenVar varSignedE regsigList ';' { $$ = $4; }
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;
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modParDecl: varRESET varGParam varSignedE regrangeE paramList { $$ = $5; } /* No semicolon*/
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;
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varRESET: /* empty */ { VARRESET(); }
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;
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@ -434,28 +465,8 @@ v2kVarDecl: v2kNetDeclE { }
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| varReg { }
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;
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v2kPort: varRESET varInput varSignedE v2kNetDeclE regrangeE v2kPortSig { $$ = $6; }
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| varRESET varInout varSignedE v2kNetDeclE regrangeE v2kPortSig { $$ = $6; }
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| varRESET varOutput varSignedE v2kVarDecl regrangeE v2kPortSig { $$ = $6; }
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;
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ioDecl: varRESET varInput varSignedE v2kNetDeclE regrangeE sigList ';' { $$ = $6; }
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| varRESET varInout varSignedE v2kNetDeclE regrangeE sigList ';' { $$ = $6; }
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| varRESET varOutput varSignedE v2kVarDecl regrangeE sigList ';' { $$ = $6; }
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;
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varDecl: varRESET varReg varSignedE regrangeE regsigList ';' { $$ = $5; }
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| varRESET varGParam varSignedE regrangeE paramList ';' { $$ = $5; }
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| varRESET varLParam varSignedE regrangeE paramList ';' { $$ = $5; }
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| varRESET varNet varSignedE delayrange netSigList ';' { $$ = $5; }
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| varRESET varGenVar varSignedE regsigList ';' { $$ = $4; }
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;
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modParDecl: varRESET varGParam varSignedE regrangeE paramList { $$ = $5; } /* No semicolon*/
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;
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//************************************************
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// modItemList
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// Module Items
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modItemListE: /* empty */ { $$ = NULL; }
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| modItemList { $$ = $1; }
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@ -497,7 +508,7 @@ modOrGenItem: yALWAYS sensitivityE stmtBlock { $$ = new AstAlways($1,$2,$3); }
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;
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//************************************************
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// genmodItemList
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// Generates
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// Because genItemList includes variable declarations, we don't need beginNamed
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genItemBlock: genItem { $$ = new AstBegin(CRELINE(),"genblk",$1); }
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@ -508,7 +519,7 @@ genTopBlock: genItemList { $$ = $1; }
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| genItemBegin { $$ = $1; }
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;
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genItemBegin: yBEGIN genItemList yEND { $$ = new AstBegin($1,"genblk",$2); }
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genItemBegin: yBEGIN genItemList yEND { $$ = new AstBegin($1,"genblk",$2); }
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| yBEGIN yEND { $$ = NULL; }
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| yBEGIN ':' yaID genItemList yEND { $$ = new AstBegin($2,*$3,$4); }
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| yBEGIN ':' yaID yEND { $$ = NULL; }
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@ -528,20 +539,16 @@ genItem: modOrGenItem { $$ = $1; }
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,$13);}
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;
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genCaseList: casecondList ':' genItemBlock { $$ = new AstCaseItem($2,$1,$3); }
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genCaseList: caseCondList ':' genItemBlock { $$ = new AstCaseItem($2,$1,$3); }
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| yDEFAULT ':' genItemBlock { $$ = new AstCaseItem($2,NULL,$3); }
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| yDEFAULT genItemBlock { $$ = new AstCaseItem($1,NULL,$2); }
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| genCaseList casecondList ':' genItemBlock { $$ = $1;$1->addNext(new AstCaseItem($3,$2,$4)); }
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| genCaseList caseCondList ':' genItemBlock { $$ = $1;$1->addNext(new AstCaseItem($3,$2,$4)); }
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| genCaseList yDEFAULT genItemBlock { $$ = $1;$1->addNext(new AstCaseItem($2,NULL,$3)); }
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| genCaseList yDEFAULT ':' genItemBlock { $$ = $1;$1->addNext(new AstCaseItem($3,NULL,$4)); }
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;
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//************************************************
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// modItems
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varDeclList: varDecl { $$ = $1; }
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| varDecl varDeclList { $$ = $1->addNext($2); }
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;
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// Assignments and register declarations
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assignList: assignOne { $$ = $1; }
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| assignList ',' assignOne { $$ = $1->addNext($3); }
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@ -552,22 +559,28 @@ assignOne: varRefDotBit '=' expr { $$ = new AstAssignW($2,$1,$3); }
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;
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delayE: /* empty */
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| '#' dterm {} /* ignored */
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| '#' '(' dterm ')' {} /* ignored */
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| '#' '(' dterm ',' dterm ')' {} /* ignored */
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| '#' '(' dterm ',' dterm ',' dterm ')' {} /* ignored */
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| '#' dlyTerm {} /* ignored */
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| '#' '(' dlyTerm ')' {} /* ignored */
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| '#' '(' dlyTerm ',' dlyTerm ')' {} /* ignored */
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| '#' '(' dlyTerm ',' dlyTerm ',' dlyTerm ')' {} /* ignored */
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;
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dterm: yaID { $$ = NULL; }
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dlyTerm: yaID { $$ = NULL; }
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| yaINTNUM { $$ = NULL; }
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| yaFLOATNUM { $$ = NULL; }
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;
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onesig: sigId { $$=$1; }
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| sigId sigAttrList { $$=$1; }
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sigAndAttr: sigId { $$ = $1; }
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| sigId sigAttrList { $$ = $1; }
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;
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sigId: yaID { $$ = V3Parse::createVariable(CRELINE(), *$1, NULL); }
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netSigList: netSig { $$ = $1; }
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| netSigList ',' netSig { $$ = $1; $1->addNext($3); }
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;
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netSig: sigId sigAttrListE { $$ = $1; }
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| sigId sigAttrListE '=' expr { $$ = $1; $1->addNext(new AstAssignW($3,new AstVarRef($3,$1->name(),true),$4)); }
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| sigIdRange sigAttrListE { $$ = $1; }
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;
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sigIdRange: yaID rangeList { $$ = V3Parse::createVariable(CRELINE(), *$1, $2); }
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@ -578,7 +591,15 @@ regSigId: yaID rangeListE { $$ = V3Parse::createVariable(CRELINE(), *$1, $2);
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$$->addNext(new AstInitial($3,new AstAssign($3, new AstVarRef($3, $$, true), $4))); }
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;
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paramId: yaID { $$ = V3Parse::createVariable(CRELINE(), *$1, NULL); }
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sigId: yaID { $$ = V3Parse::createVariable(CRELINE(), *$1, NULL); }
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;
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sigList: sigAndAttr { $$ = $1; }
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| sigList ',' sigAndAttr { $$ = $1; $1->addNext($3); }
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;
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regsig: regSigId {}
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| regSigId sigAttrList {}
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;
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sigAttrListE: /*empty*/ {}
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@ -596,27 +617,6 @@ sigAttr: yVL_CLOCK { V3Parse::s_varAttrp->attrScClocked(true); }
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| yVL_ISOLATE_ASSIGNMENTS { V3Parse::s_varAttrp->attrIsolateAssign(true); }
|
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;
|
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sigList: onesig { $$ = $1; }
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| sigList ',' onesig { $$ = $1; $1->addNext($3); }
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;
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netSig: sigId sigAttrListE { $$ = $1; }
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| sigId sigAttrListE '=' expr { $$ = $1; $1->addNext(new AstAssignW($3,new AstVarRef($3,$1->name(),true),$4)); }
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| sigIdRange sigAttrListE { $$ = $1; }
|
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;
|
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netSigList: netSig { $$ = $1; }
|
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| netSigList ',' netSig { $$ = $1;$1->addNext($3); }
|
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;
|
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|
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regsig: regSigId {}
|
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| regSigId sigAttrList {}
|
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;
|
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|
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regsigList: regsig { $$ = $1; }
|
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| regsigList ',' regsig { $$ = $1;$1->addNext($3); }
|
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;
|
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rangeListE: /* empty */ { $$ = NULL; }
|
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| rangeList { $$ = $1; }
|
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;
|
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@ -637,13 +637,15 @@ delayrange: delayE regrangeE { $$ = $2; }
|
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| yVECTORED delayE regrangeE { $$ = $3; }
|
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;
|
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|
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portrangeE: /* empty */ { $$ = NULL; }
|
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portRangeE: /* empty */ { $$ = NULL; }
|
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| '[' constExpr ']' { $$ = NULL; $1->v3error("Ranges ignored on port-list.\n"); }
|
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| '[' constExpr ':' constExpr ']' { $$ = NULL; $1->v3error("Ranges ignored on port-list.\n"); }
|
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;
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|
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//************************************************
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// Parameters
|
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param: paramId sigAttrListE '=' expr { $$ = $1; $$->initp($4); }
|
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|
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param: sigId sigAttrListE '=' expr { $$ = $1; $$->initp($4); }
|
||||
;
|
||||
|
||||
paramList: param { $$ = $1; }
|
||||
@ -657,7 +659,9 @@ defpList: defpOne { $$ = $1; }
|
||||
defpOne: yaID '.' yaID '=' expr { $$ = new AstDefParam($4,*$1,*$3,$5); }
|
||||
;
|
||||
|
||||
//************************************************
|
||||
// Instances
|
||||
|
||||
instparamListE: /* empty */ { $$ = NULL; }
|
||||
| '#' '(' cellpinList ')' { $$ = $3; }
|
||||
;
|
||||
@ -666,14 +670,14 @@ instnameList: instname { $$ = $1; }
|
||||
| instnameList ',' instname { $$ = $1->addNext($3); }
|
||||
;
|
||||
|
||||
instname: yaID funcRange '(' cellpinList ')' { $$ = new AstCell($3,*$1,V3Parse::s_instModule,$4,V3Parse::s_instParamp,$2); $$->pinStar(V3Parse::s_pinStar); }
|
||||
instname: yaID funcRangeE '(' cellpinList ')' { $$ = new AstCell($3,*$1,V3Parse::s_instModule,$4,V3Parse::s_instParamp,$2); $$->pinStar(V3Parse::s_pinStar); }
|
||||
;
|
||||
|
||||
cellpinList: {V3Parse::s_pinNum=1; V3Parse::s_pinStar=false; } cellpinlist2 { $$ = $2; }
|
||||
cellpinList: {V3Parse::s_pinNum=1; V3Parse::s_pinStar=false; } cellpinItList { $$ = $2; }
|
||||
;
|
||||
|
||||
cellpinlist2: cellpinitemE { $$ = $1; }
|
||||
| cellpinlist2 ',' cellpinitemE { $$ = $1->addNextNull($3)->castPin(); }
|
||||
cellpinItList: cellpinitemE { $$ = $1; }
|
||||
| cellpinItList ',' cellpinitemE { $$ = $1->addNextNull($3)->castPin(); }
|
||||
;
|
||||
|
||||
cellpinitemE: /* empty */ { $$ = NULL; V3Parse::s_pinNum++; }
|
||||
@ -684,6 +688,9 @@ cellpinitemE: /* empty */ { $$ = NULL; V3Parse::s_pinNum++; }
|
||||
| expr { $$ = new AstPin(CRELINE(),V3Parse::s_pinNum++,"",$1); }
|
||||
;
|
||||
|
||||
//************************************************
|
||||
// Sensitivity lists
|
||||
|
||||
sensitivityE: /* empty */ { $$ = NULL; }
|
||||
| '@' '(' senList ')' { $$ = new AstSenTree($1,$3); }
|
||||
| '@' senitem { $$ = new AstSenTree($1,$2); }
|
||||
@ -697,7 +704,6 @@ senList: senitem { $$ = $1; }
|
||||
;
|
||||
|
||||
senitem: senitemEdge { $$ = $1; }
|
||||
//FIX need range ignoring to be stripped later, this was simple varXRef
|
||||
| varRefDotBit { $$ = new AstSenItem(CRELINE(),AstEdgeType::ANYEDGE,$1); }
|
||||
;
|
||||
|
||||
@ -705,6 +711,9 @@ senitemEdge: yPOSEDGE varRefDotBit { $$ = new AstSenItem($1,AstEdgeType::POSED
|
||||
| yNEGEDGE varRefDotBit { $$ = new AstSenItem($1,AstEdgeType::NEGEDGE,$2); }
|
||||
;
|
||||
|
||||
//************************************************
|
||||
// Statements
|
||||
|
||||
stmtBlock: stmt { $$ = $1; }
|
||||
| yBEGIN stmtList yEND { $$ = $2; }
|
||||
| yBEGIN yEND { $$ = NULL; }
|
||||
@ -759,11 +768,10 @@ stmt: ';' { $$ = NULL; }
|
||||
| yD_READMEMH '(' expr ',' varRefMem ')' ';' { $$ = new AstReadMem($1,true, $3,$5,NULL,NULL); }
|
||||
| yD_READMEMH '(' expr ',' varRefMem ',' expr ')' ';' { $$ = new AstReadMem($1,true, $3,$5,$7,NULL); }
|
||||
| yD_READMEMH '(' expr ',' varRefMem ',' expr ',' expr ')' ';' { $$ = new AstReadMem($1,true, $3,$5,$7,$9); }
|
||||
|
||||
;
|
||||
|
||||
labeledStmt: assertStmt { $$ = $1; }
|
||||
;
|
||||
//************************************************
|
||||
// Case/If
|
||||
|
||||
stateCaseForIf: caseStmt caseAttrE caseList yENDCASE { $$ = $1; $1->addItemsp($3); }
|
||||
| yIF expr stmtBlock %prec prLOWER_THAN_ELSE { $$ = new AstIf($1,$2,$3,NULL); }
|
||||
@ -776,11 +784,6 @@ stateCaseForIf: caseStmt caseAttrE caseList yENDCASE { $$ = $1; $1->addItemsp($3
|
||||
| yDO stmtBlock yWHILE '(' expr ')' { $$ = $2->cloneTree(true); $$->addNext(new AstWhile($1,$5,$2));}
|
||||
;
|
||||
|
||||
assertStmt: yASSERT '(' expr ')' stmtBlock %prec prLOWER_THAN_ELSE { $$ = new AstVAssert($1,$3,$5, V3Parse::createDisplayError($1)); }
|
||||
| yASSERT '(' expr ')' yELSE stmtBlock { $$ = new AstVAssert($1,$3,NULL,$6); }
|
||||
| yASSERT '(' expr ')' stmtBlock yELSE stmtBlock { $$ = new AstVAssert($1,$3,$5,$7); }
|
||||
;
|
||||
|
||||
caseStmt: yCASE '(' expr ')' { $$ = V3Parse::s_caseAttrp = new AstCase($1,false,$3,NULL); }
|
||||
| yCASEX '(' expr ')' { $$ = V3Parse::s_caseAttrp = new AstCase($1,true,$3,NULL); $1->v3warn(CASEX,"Suggest casez (with ?'s) in place of casex (with X's)\n"); }
|
||||
| yCASEZ '(' expr ')' { $$ = V3Parse::s_caseAttrp = new AstCase($1,true,$3,NULL); }
|
||||
@ -791,33 +794,43 @@ caseAttrE: /*empty*/ { }
|
||||
| caseAttrE yVL_PARALLEL_CASE { V3Parse::s_caseAttrp->parallelPragma(true); }
|
||||
;
|
||||
|
||||
caseList: casecondList ':' stmtBlock { $$ = new AstCaseItem($2,$1,$3); }
|
||||
caseList: caseCondList ':' stmtBlock { $$ = new AstCaseItem($2,$1,$3); }
|
||||
| yDEFAULT ':' stmtBlock { $$ = new AstCaseItem($2,NULL,$3); }
|
||||
| yDEFAULT stmtBlock { $$ = new AstCaseItem($1,NULL,$2); }
|
||||
| caseList casecondList ':' stmtBlock { $$ = $1;$1->addNext(new AstCaseItem($3,$2,$4)); }
|
||||
| caseList caseCondList ':' stmtBlock { $$ = $1;$1->addNext(new AstCaseItem($3,$2,$4)); }
|
||||
| caseList yDEFAULT stmtBlock { $$ = $1;$1->addNext(new AstCaseItem($2,NULL,$3)); }
|
||||
| caseList yDEFAULT ':' stmtBlock { $$ = $1;$1->addNext(new AstCaseItem($3,NULL,$4)); }
|
||||
;
|
||||
|
||||
casecondList: expr { $$ = $1; }
|
||||
| casecondList ',' expr { $$ = $1;$1->addNext($3); }
|
||||
caseCondList: expr { $$ = $1; }
|
||||
| caseCondList ',' expr { $$ = $1;$1->addNext($3); }
|
||||
;
|
||||
|
||||
//************************************************
|
||||
// Functions/tasks
|
||||
|
||||
taskRef: idDotted { $$ = new AstTaskRef(CRELINE(),new AstParseRef($1->fileline(), AstParseRefExp::TASK, $1),NULL);}
|
||||
| idDotted '(' exprList ')' { $$ = new AstTaskRef(CRELINE(),new AstParseRef($1->fileline(), AstParseRefExp::TASK, $1),$3);}
|
||||
;
|
||||
|
||||
funcRef: idDotted '(' exprList ')' { $$ = new AstFuncRef($2,new AstParseRef($1->fileline(), AstParseRefExp::FUNC, $1), $3); }
|
||||
;
|
||||
|
||||
taskDecl: yTASK yaID ';' stmtBlock yENDTASK { $$ = new AstTask ($1,*$2,$4);}
|
||||
| yTASK yaID ';' funcVarList stmtBlock yENDTASK { $$ = new AstTask ($1,*$2,$4); $4->addNextNull($5); }
|
||||
;
|
||||
|
||||
funcDecl: yFUNCTION funcRange yaID ';' funcBody yENDFUNCTION { $$ = new AstFunc ($1,*$3,$5,$2); }
|
||||
| yFUNCTION ySIGNED funcRange yaID ';' funcBody yENDFUNCTION { $$ = new AstFunc ($1,*$4,$6,$3); $$->isSigned(true); }
|
||||
| yFUNCTION funcRange yaID yVL_ISOLATE_ASSIGNMENTS ';' funcBody yENDFUNCTION { $$ = new AstFunc ($1,*$3,$6,$2); $$->attrIsolateAssign(true);}
|
||||
| yFUNCTION ySIGNED funcRange yaID yVL_ISOLATE_ASSIGNMENTS ';' funcBody yENDFUNCTION { $$ = new AstFunc ($1,*$4,$7,$3); $$->attrIsolateAssign(true); $$->isSigned(true); }
|
||||
funcDecl: yFUNCTION funcRangeE yaID ';' funcBody yENDFUNCTION { $$ = new AstFunc ($1,*$3,$5,$2); }
|
||||
| yFUNCTION ySIGNED funcRangeE yaID ';' funcBody yENDFUNCTION { $$ = new AstFunc ($1,*$4,$6,$3); $$->isSigned(true); }
|
||||
| yFUNCTION funcRangeE yaID yVL_ISOLATE_ASSIGNMENTS ';' funcBody yENDFUNCTION { $$ = new AstFunc ($1,*$3,$6,$2); $$->attrIsolateAssign(true);}
|
||||
| yFUNCTION ySIGNED funcRangeE yaID yVL_ISOLATE_ASSIGNMENTS ';' funcBody yENDFUNCTION { $$ = new AstFunc ($1,*$4,$7,$3); $$->attrIsolateAssign(true); $$->isSigned(true); }
|
||||
;
|
||||
|
||||
funcBody: funcVarList stmtBlock { $$ = $1;$1->addNextNull($2); }
|
||||
;
|
||||
|
||||
funcRange: '[' constExpr ':' constExpr ']' { $$ = new AstRange($1,$2,$4); }
|
||||
| { $$ = NULL; }
|
||||
funcRangeE: /* empty */ { $$ = NULL; }
|
||||
| '[' constExpr ':' constExpr ']' { $$ = new AstRange($1,$2,$4); }
|
||||
;
|
||||
|
||||
funcVarList: funcVar { $$ = $1; }
|
||||
@ -830,6 +843,9 @@ funcVar: ioDecl { $$ = $1; }
|
||||
| yVL_NO_INLINE_TASK { $$ = new AstPragma($1,AstPragmaType::NO_INLINE_TASK); }
|
||||
;
|
||||
|
||||
//************************************************
|
||||
// Expressions
|
||||
|
||||
constExpr: expr { $$ = $1; }
|
||||
;
|
||||
|
||||
@ -919,15 +935,17 @@ cateList: expr { $$ = $1; }
|
||||
| cateList ',' expr { $$ = new AstConcat($2,$1,$3); }
|
||||
;
|
||||
|
||||
eList: expr { $$ = $1; }
|
||||
| eList ',' expr { $$ = $1;$1->addNext($3); }
|
||||
exprList: expr { $$ = $1; }
|
||||
| exprList ',' expr { $$ = $1;$1->addNext($3); }
|
||||
;
|
||||
|
||||
commaEListE: /* empty */ { $$ = NULL; }
|
||||
| ',' eList { $$ = $2; }
|
||||
| ',' exprList { $$ = $2; }
|
||||
;
|
||||
|
||||
//************************************************
|
||||
// Gate declarations
|
||||
|
||||
gateDecl: yBUF gateBufList ';' { $$ = $2; }
|
||||
| yNOT gateNotList ';' { $$ = $2; }
|
||||
| yAND gateAndList ';' { $$ = $2; }
|
||||
@ -963,10 +981,6 @@ gateXnorList: gateXnor { $$ = $1; }
|
||||
| gateXnor ',' gateXnor { $$ = $1->addNext($3); }
|
||||
;
|
||||
|
||||
gateIdE: /*empty*/ {}
|
||||
| yaID {}
|
||||
;
|
||||
|
||||
gateBuf: gateIdE '(' varRefDotBit ',' expr ')' { $$ = new AstAssignW ($2,$3,$5); $$->allowImplicit(true); }
|
||||
;
|
||||
gateNot: gateIdE '(' varRefDotBit ',' expr ')' { $$ = new AstAssignW ($2,$3,new AstNot($4,$5)); $$->allowImplicit(true); }
|
||||
@ -984,6 +998,10 @@ gateXor: gateIdE '(' varRefDotBit ',' gateXorPinList ')' { $$ = new AstAssignW (
|
||||
gateXnor: gateIdE '(' varRefDotBit ',' gateXorPinList ')' { $$ = new AstAssignW ($2,$3,new AstNot($4,$5)); $$->allowImplicit(true); }
|
||||
;
|
||||
|
||||
gateIdE: /*empty*/ {}
|
||||
| yaID {}
|
||||
;
|
||||
|
||||
gateAndPinList: expr { $$ = $1; }
|
||||
| gateAndPinList ',' expr { $$ = new AstAnd($2,$1,$3); }
|
||||
;
|
||||
@ -996,11 +1014,12 @@ gateXorPinList: expr { $$ = $1; }
|
||||
|
||||
//************************************************
|
||||
// Specify
|
||||
|
||||
specifyJunkList: specifyJunk /* ignored */
|
||||
| specifyJunkList specifyJunk /* ignored */
|
||||
;
|
||||
|
||||
specifyJunk: dterm {} /* ignored */
|
||||
specifyJunk: dlyTerm {} /* ignored */
|
||||
| ';' {}
|
||||
| '!' {}
|
||||
| '&' {}
|
||||
@ -1045,24 +1064,6 @@ specifyJunk: dterm {} /* ignored */
|
||||
//************************************************
|
||||
// IDs
|
||||
|
||||
// Single component of dotted path, maybe [#].
|
||||
// Due to lookahead constraints, we can't know if [:] or [+:] are valid (last dotted part),
|
||||
// we'll assume so and cleanup later.
|
||||
idArrayed: yaID { $$ = new AstText(CRELINE(),*$1); }
|
||||
| idArrayed '[' expr ']' { $$ = new AstSelBit($2,$1,$3); } // Or AstArraySel, don't know yet.
|
||||
| idArrayed '[' constExpr ':' constExpr ']' { $$ = new AstSelExtract($2,$1,$3,$5); }
|
||||
| idArrayed '[' expr yP_PLUSCOLON constExpr ']' { $$ = new AstSelPlus($2,$1,$3,$5); }
|
||||
| idArrayed '[' expr yP_MINUSCOLON constExpr ']' { $$ = new AstSelMinus($2,$1,$3,$5); }
|
||||
;
|
||||
|
||||
idDotted: idArrayed { $$ = $1; }
|
||||
| idDotted '.' idArrayed { $$ = new AstDot($2,$1,$3); }
|
||||
;
|
||||
|
||||
// VarRef without any dots or vectorizaion
|
||||
varRefBase: yaID { $$ = new AstVarRef(CRELINE(),*$1,false);}
|
||||
;
|
||||
|
||||
// VarRef to a Memory
|
||||
varRefMem: idDotted { $$ = new AstParseRef($1->fileline(), AstParseRefExp::VAR_MEM, $1); }
|
||||
;
|
||||
@ -1071,11 +1072,22 @@ varRefMem: idDotted { $$ = new AstParseRef($1->fileline(), AstParseRefExp::VA
|
||||
varRefDotBit: idDotted { $$ = new AstParseRef($1->fileline(), AstParseRefExp::VAR_ANY, $1); }
|
||||
;
|
||||
|
||||
taskRef: idDotted { $$ = new AstTaskRef(CRELINE(),new AstParseRef($1->fileline(), AstParseRefExp::TASK, $1),NULL);}
|
||||
| idDotted '(' eList ')' { $$ = new AstTaskRef(CRELINE(),new AstParseRef($1->fileline(), AstParseRefExp::TASK, $1),$3);}
|
||||
idDotted: idArrayed { $$ = $1; }
|
||||
| idDotted '.' idArrayed { $$ = new AstDot($2,$1,$3); }
|
||||
;
|
||||
|
||||
funcRef: idDotted '(' eList ')' { $$ = new AstFuncRef($2,new AstParseRef($1->fileline(), AstParseRefExp::FUNC, $1), $3); }
|
||||
// Single component of dotted path, maybe [#].
|
||||
// Due to lookahead constraints, we can't know if [:] or [+:] are valid (last dotted part),
|
||||
// we'll assume so and cleanup later.
|
||||
idArrayed: yaID { $$ = new AstText(CRELINE(),*$1); }
|
||||
| idArrayed '[' expr ']' { $$ = new AstSelBit($2,$1,$3); } // Or AstArraySel, don't know yet.
|
||||
| idArrayed '[' constExpr ':' constExpr ']' { $$ = new AstSelExtract($2,$1,$3,$5); }
|
||||
| idArrayed '[' expr yP_PLUSCOLON constExpr ']' { $$ = new AstSelPlus($2,$1,$3,$5); }
|
||||
| idArrayed '[' expr yP_MINUSCOLON constExpr ']' { $$ = new AstSelMinus($2,$1,$3,$5); }
|
||||
;
|
||||
|
||||
// VarRef without any dots or vectorizaion
|
||||
varRefBase: yaID { $$ = new AstVarRef(CRELINE(),*$1,false);}
|
||||
;
|
||||
|
||||
strAsInt: yaSTRING { $$ = new AstConst(CRELINE(),V3Number(V3Number::VerilogString(),CRELINE(),V3Parse::deQuote(CRELINE(),*$1)));}
|
||||
@ -1088,6 +1100,17 @@ concIdList: varRefDotBit { $$ = $1; }
|
||||
| concIdList ',' varRefDotBit { $$ = new AstConcat($2,$1,$3); }
|
||||
;
|
||||
|
||||
//************************************************
|
||||
// Asserts
|
||||
|
||||
labeledStmt: assertStmt { $$ = $1; }
|
||||
;
|
||||
|
||||
assertStmt: yASSERT '(' expr ')' stmtBlock %prec prLOWER_THAN_ELSE { $$ = new AstVAssert($1,$3,$5, V3Parse::createDisplayError($1)); }
|
||||
| yASSERT '(' expr ')' yELSE stmtBlock { $$ = new AstVAssert($1,$3,NULL,$6); }
|
||||
| yASSERT '(' expr ')' stmtBlock yELSE stmtBlock { $$ = new AstVAssert($1,$3,$5,$7); }
|
||||
;
|
||||
|
||||
//************************************************
|
||||
// PSL Statements
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user