From b2070a9407ee5cc7516b3c2552632cee1cf3e7cc Mon Sep 17 00:00:00 2001
From: Geza Lore <gezalore@gmail.com>
Date: Tue, 11 Oct 2022 10:06:05 +0100
Subject: [PATCH] Commentary: Mention DFG in changes

---
 Changes | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Changes b/Changes
index 45bbdb2b2..bdb6af7f9 100644
--- a/Changes
+++ b/Changes
@@ -19,6 +19,8 @@ Verilator 5.001 devel
   clocks are now simulated correctly (#3278, #3384). [Geza Lore, Shunyao CAD]
 * Support timing controls (delays, event controls in any location, wait
   statements) and forks. See docs for details. [Krzysztof Bieganski, Antmicro Ltd]
+* Introduce a new combinational logic optimizer (DFG), that can yield
+  significant performance improvements on some designs. [Geza Lore, Shunyao CAD]
 * Add --binary option as alias of --main --exe --build --timing (#3625).