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In warnings, rename cells to instances to match IEEE
This commit is contained in:
Wilson Snyder
parent
53c4c7d540
commit
b04a1caeac
@ -1639,8 +1639,8 @@ into Verilator. (Similar to perl -V.) See also --getenv.
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=item -v I<filename>
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Read the filename as a Verilog library. Any modules in the file may be
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used to resolve cell instantiations in the top level module, else ignored.
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Note -v is fairly standard across Verilog tools.
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used to resolve instances in the top level module, else ignored. Note -v
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is fairly standard across Verilog tools.
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=item --no-verilate
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@ -3104,8 +3104,8 @@ Enable/disable waveform tracing for all future signals declared in the
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specified filename (or wildcard with '*' or '?', or all files if omitted)
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and range of line numbers (or all lines if omitted).
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For tracing_off, cells below any module in the files/ranges specified will
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also not be traced.
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For tracing_off, instances below any module in the files/ranges specified
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will also not be traced.
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=item clock_enable -module "<modulename>" -var "<signame>"
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@ -3777,13 +3777,13 @@ for use by downstream applications.
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=item /*verilator tracing_off*/
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Disable waveform tracing for all future signals that are declared in this
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module, or cells below this module. Often this is placed just after a
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primitive's module statement, so that the entire module and cells below it
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are not traced.
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module, or instances below this module. Often this is placed just after a
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primitive's module statement, so that the entire module and instances below
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it are not traced.
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=item /*verilator tracing_on*/
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Re-enable waveform tracing for all future signals or cells that are
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Re-enable waveform tracing for all future signals or instances that are
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declared.
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=back
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@ -3837,8 +3837,8 @@ for example a[2].b is acceptable, while a[x].b is generally not.
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References into generated and arrayed instances use the instance names
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specified in the Verilog standard; arrayed instances are named
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{cellName}[{instanceNumber}] in Verilog, which becomes
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{cellname}__BRA__{instanceNumber}__KET__ inside the generated C++ code.
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{instanceName}[{instanceNumber}] in Verilog, which becomes
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{instanceName}__BRA__{instanceNumber}__KET__ inside the generated C++ code.
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=head2 Latches
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@ -4523,9 +4523,9 @@ top module statement is processed.
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Warns that a wire is being implicitly declared (it is a single bit wide
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output from a sub-module.) While legal in Verilog, implicit declarations
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only work for single bit wide signals (not buses), do not allow using a
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signal before it is implicitly declared by a cell, and can lead to dangling
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nets. A better option is the /*AUTOWIRE*/ feature of Verilog-Mode for
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Emacs, available from L<https://www.veripool.org/verilog-mode>
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signal before it is implicitly declared by an instance, and can lead to
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dangling nets. A better option is the /*AUTOWIRE*/ feature of Verilog-Mode
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for Emacs, available from L<https://www.veripool.org/verilog-mode>
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Ignoring this warning will only suppress the lint check, it will simulate
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correctly.
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@ -4598,10 +4598,10 @@ Warns that a packed vector is declared with little endian bit numbering
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and little numbering is now thus often due to simple oversight instead of
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intent.
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Also warns that a cell is declared with little endian range (i.e. [0:7] or
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[7]) and is connected to a N-wide signal. Based on IEEE the bits will
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likely be backwards from what you expect (i.e. cell [0] will connect to
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signal bit [N-1] not bit [0]).
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Also warns that an instance is declared with little endian range
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(i.e. [0:7] or [7]) and is connected to a N-wide signal. Based on IEEE the
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bits will likely be backwards from what you expect (i.e. instance [0] will
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connect to signal bit [N-1] not bit [0]).
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Ignoring this warning will only suppress the lint check, it will simulate
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correctly.
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@ -4633,10 +4633,10 @@ instantiated by any other module, and both modules were put on the command
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line (not in a library). Three likely cases:
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1. A single module is intended to be the top. This warning then occurs
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because some low level cell is being read in, but is not really needed as
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part of the design. The best solution for this situation is to ensure that
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only the top module is put on the command line without any flags, and all
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remaining library files are read in as libraries with -v, or are
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because some low level instance is being read in, but is not really needed
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as part of the design. The best solution for this situation is to ensure
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that only the top module is put on the command line without any flags, and
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all remaining library files are read in as libraries with -v, or are
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automatically resolved by having filenames that match the module names.
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2. A single module is intended to be the top, the name of it is known, and
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@ -4656,27 +4656,26 @@ identical, e.g. multiple modules with a "clk" input.
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=item PINCONNECTEMPTY
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Warns that a cell instantiation has a pin which is connected to
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.pin_name(), e.g. not another signal, but with an explicit mention of the
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pin. It may be desirable to disable PINCONNECTEMPTY, as this indicates
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intention to have a no-connect.
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Warns that an instance has a pin which is connected to .pin_name(),
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e.g. not another signal, but with an explicit mention of the pin. It may
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be desirable to disable PINCONNECTEMPTY, as this indicates intention to
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have a no-connect.
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Disabled by default as this is a code style warning; it will simulate
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correctly.
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=item PINMISSING
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Warns that a module has a pin which is not mentioned in a cell
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instantiation. If a pin is not missing it should still be specified on the
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cell declaration with a empty connection, using "(.pin_name())".
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Warns that a module has a pin which is not mentioned in an instance. If a
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pin is not missing it should still be specified on the instance declaration
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with a empty connection, using "(.pin_name())".
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Ignoring this warning will only suppress the lint check, it will simulate
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correctly.
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=item PINNOCONNECT
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Warns that a cell instantiation has a pin which is not connected to another
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signal.
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Warns that an instance has a pin which is not connected to another signal.
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Disabled by default as this is a code style warning; it will simulate
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correctly.
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@ -4919,7 +4918,7 @@ potentially resolving the conflict. If you run with --report-unoptflat
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Verilator will suggest possible candidates for C<split_var>.
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The UNOPTFLAT warning may also be due to clock enables, identified from the
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reported path going through a clock gating cell. To fix these, use the
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reported path going through a clock gating instance. To fix these, use the
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clock_enable meta comment described above.
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The UNOPTFLAT warning may also occur where outputs from a block of logic
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@ -5494,21 +5493,21 @@ by your code or you'll get strange results.
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=item Should a module be in Verilog or SystemC?
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Sometimes there is a block that just interconnects cells, and have a choice
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as to if you write it in Verilog or SystemC. Everything else being equal,
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best performance is when Verilator sees all of the design. So, look at the
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hierarchy of your design, labeling cells as to if they are SystemC or
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Verilog. Then:
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Sometimes there is a block that just interconnects instances, and have a
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choice as to if you write it in Verilog or SystemC. Everything else being
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equal, best performance is when Verilator sees all of the design. So, look
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at the hierarchy of your design, labeling instances as to if they are
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SystemC or Verilog. Then:
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A module with only SystemC cells below must be SystemC.
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A module with only SystemC instances below must be SystemC.
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A module with a mix of Verilog and SystemC cells below must be SystemC. (As
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Verilator cannot connect to lower-level SystemC cells.)
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A module with a mix of Verilog and SystemC instances below must be
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SystemC. (As Verilator cannot connect to lower-level SystemC instances.)
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A module with only Verilog cells below can be either, but for best
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A module with only Verilog instances below can be either, but for best
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performance should be Verilog. (The exception is if you have a design that
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is instantiated many times; in this case Verilating one of the lower
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modules and instantiating that Verilated cells multiple times into a
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modules and instantiating that Verilated instances multiple times into a
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SystemC module *may* be faster.)
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=back
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@ -2940,7 +2940,7 @@ public:
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AstBind(FileLine* fl, const string& name, AstNode* cellsp)
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: ASTGEN_SUPER(fl)
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, m_name{name} {
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UASSERT_OBJ(VN_IS(cellsp, Cell), cellsp, "Only cells allowed to be bound");
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UASSERT_OBJ(VN_IS(cellsp, Cell), cellsp, "Only instances allowed to be bound");
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addNOp1p(cellsp);
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}
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ASTNODE_NODE_FUNCS(Bind)
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@ -123,7 +123,7 @@ private:
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hierUnprot = v3Global.opt.modPrefix() + "_"; // Prefix before protected part
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return scopep->modp()->name() + "::";
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} else if (relativeRefOk && scopep->aboveScopep() && scopep->aboveScopep() == m_scopep) {
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// Reference to scope of cell directly under this module, can just "cell->"
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// Reference to scope of instance directly under this module, can just "cell->"
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string name = scopep->name();
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string::size_type pos;
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if ((pos = name.rfind('.')) != string::npos) name.erase(0, pos + 1);
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@ -614,7 +614,7 @@ public:
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// CONSTRUCTORS
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explicit InlineVisitor(AstNode* nodep) { iterate(nodep); }
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virtual ~InlineVisitor() override { //
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V3Stats::addStat("Optimizations, Inlined cells", m_statCells);
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V3Stats::addStat("Optimizations, Inlined instances", m_statCells);
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}
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};
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@ -341,8 +341,8 @@ private:
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// Arrayed instants: one bit for each of the instants (each
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// assign is 1 pinwidth wide)
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if (m_cellRangep->littleEndian()) {
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nodep->exprp()->v3warn(LITENDIAN, "Little endian cell range connecting to "
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"vector: left < right of cell range: ["
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nodep->exprp()->v3warn(LITENDIAN, "Little endian instance range connecting to "
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"vector: left < right of instance range: ["
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<< m_cellRangep->leftConst() << ":"
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<< m_cellRangep->rightConst() << "]");
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}
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@ -183,7 +183,7 @@ private:
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}
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v3error("Specified --top-module '"
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<< v3Global.opt.topModule()
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<< "' isn't at the top level, it's under another cell '"
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<< "' isn't at the top level, it's under another instance '"
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<< (abovep ? abovep->prettyName() : "UNKNOWN") << "'");
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}
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}
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@ -363,7 +363,7 @@ private:
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for (AstPin *nextp, *pinp = nodep->pinsp(); pinp; pinp = nextp) {
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nextp = VN_CAST(pinp->nextp(), Pin);
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if (pinp->dotStar()) {
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if (pinStar) pinp->v3error("Duplicate .* in a cell");
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if (pinStar) pinp->v3error("Duplicate .* in an instance");
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pinStar = true;
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// Done with this fake pin
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VL_DO_DANGLING(pinp->unlinkFrBack()->deleteTree(), pinp);
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@ -383,7 +383,7 @@ private:
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std::unordered_set<string> ports; // Symbol table of all connected port names
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for (AstPin* pinp = nodep->pinsp(); pinp; pinp = VN_CAST(pinp->nextp(), Pin)) {
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if (pinp->name() == "")
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pinp->v3error("Connect by position is illegal in .* connected cells");
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pinp->v3error("Connect by position is illegal in .* connected instances");
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if (!pinp->exprp()) {
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if (pinp->name().substr(0, 11) == "__pinNumber") {
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pinp->v3warn(PINNOCONNECT,
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@ -225,7 +225,7 @@ public:
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if (VN_IS(nodep, Var)) {
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return "variable";
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} else if (VN_IS(nodep, Cell)) {
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return "cell";
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return "instance";
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} else if (VN_IS(nodep, Task)) {
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return "task";
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} else if (VN_IS(nodep, Func)) {
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@ -459,7 +459,7 @@ public:
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ifacerefp->v3fatalSrc("Unlinked interface");
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}
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} else if (ifacerefp->ifaceViaCellp()->dead()) {
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ifacerefp->v3error("Parent cell's interface is not found: "
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ifacerefp->v3error("Parent instance's interface is not found: "
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<< AstNode::prettyNameQ(ifacerefp->ifaceName()));
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continue;
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}
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@ -795,7 +795,7 @@ class LinkDotFindVisitor final : public AstNVisitor {
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<< AstNode::prettyNameQ(nodep->origName()));
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} else if (doit) {
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UINFO(4, " Link Module: " << nodep << endl);
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UASSERT_OBJ(!nodep->dead(), nodep, "Module in cell tree mislabeled as dead?");
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UASSERT_OBJ(!nodep->dead(), nodep, "Module in instance tree mislabeled as dead?");
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VSymEnt* upperSymp = m_curSymp ? m_curSymp : m_statep->rootEntp();
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AstPackage* pkgp = VN_CAST(nodep, Package);
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m_classOrPackagep = pkgp;
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@ -898,8 +898,8 @@ class LinkDotFindVisitor final : public AstNVisitor {
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VSymEnt* okSymp;
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aboveSymp = m_statep->findDotted(nodep->fileline(), aboveSymp, scope, baddot, okSymp);
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UASSERT_OBJ(aboveSymp, nodep,
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"Can't find cell insertion point at " << AstNode::prettyNameQ(baddot)
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<< " in: " << nodep->prettyNameQ());
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"Can't find instance insertion point at "
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<< AstNode::prettyNameQ(baddot) << " in: " << nodep->prettyNameQ());
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}
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{
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m_scope = m_scope + "." + nodep->name();
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@ -1399,7 +1399,7 @@ private:
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VSymEnt* foundp = m_statep->getNodeSym(nodep)->findIdFallback(nodep->path());
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AstCell* cellp = foundp ? VN_CAST(foundp->nodep(), Cell) : nullptr;
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if (!cellp) {
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nodep->v3error("In defparam, cell " << nodep->path() << " never declared");
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nodep->v3error("In defparam, instance " << nodep->path() << " never declared");
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} else {
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AstNode* exprp = nodep->rhsp()->unlinkFrBack();
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UINFO(9, "Defparam cell " << nodep->path() << "." << nodep->name() << " attach-to "
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@ -1558,10 +1558,11 @@ class LinkDotScopeVisitor final : public AstNVisitor {
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VSymEnt* okSymp;
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VSymEnt* cellSymp = m_statep->findDotted(nodep->fileline(), m_modSymp, ifcellname,
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baddot, okSymp);
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UASSERT_OBJ(cellSymp, nodep,
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"No symbol for interface cell: " << nodep->prettyNameQ(ifcellname));
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UINFO(5, " Found interface cell: se" << cvtToHex(cellSymp) << " "
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<< cellSymp->nodep() << endl);
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UASSERT_OBJ(
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cellSymp, nodep,
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"No symbol for interface instance: " << nodep->prettyNameQ(ifcellname));
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UINFO(5, " Found interface instance: se" << cvtToHex(cellSymp) << " "
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<< cellSymp->nodep() << endl);
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if (dtypep->modportName() != "") {
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VSymEnt* mpSymp = m_statep->findDotted(nodep->fileline(), m_modSymp,
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ifcellname, baddot, okSymp);
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@ -2007,7 +2008,7 @@ private:
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checkNoDot(nodep);
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iterateChildren(nodep);
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if (!nodep->modVarp()) {
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UASSERT_OBJ(m_pinSymp, nodep, "Pin not under cell?");
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UASSERT_OBJ(m_pinSymp, nodep, "Pin not under instance?");
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VSymEnt* foundp = m_pinSymp->findIdFlat(nodep->name());
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const char* whatp = nodep->param() ? "parameter pin" : "pin";
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if (!foundp) {
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@ -2345,7 +2346,7 @@ private:
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<< modportp->prettyNameQ());
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} else {
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AstCell* cellp = VN_CAST(m_ds.m_dotSymp->nodep(), Cell);
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UASSERT_OBJ(cellp, nodep, "Modport not referenced from a cell");
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UASSERT_OBJ(cellp, nodep, "Modport not referenced from an instance");
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VSymEnt* cellEntp = m_statep->getNodeSym(cellp);
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UASSERT_OBJ(cellEntp, nodep, "No interface sym entry");
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VSymEnt* parentEntp = cellEntp->parentp(); // Container of the var; probably a
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@ -2751,8 +2752,8 @@ private:
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if (nodep->user3SetOnce()) return;
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if (m_ds.m_dotPos
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== DP_SCOPE) { // Already under dot, so this is {modulepart} DOT {modulepart}
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nodep->v3error("Syntax Error: Range ':', '+:' etc are not allowed in the cell part of "
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"a dotted reference");
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nodep->v3error("Syntax Error: Range ':', '+:' etc are not allowed in the instance "
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"part of a dotted reference");
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m_ds.m_dotErr = true;
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return;
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}
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@ -95,14 +95,15 @@ AstRange* V3ParseGrammar::scrubRange(AstNodeRange* nrangep) {
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nextp = VN_CAST(nodep->nextp(), NodeRange);
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if (!VN_IS(nodep, Range)) {
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nodep->v3error(
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"Unsupported or syntax error: Unsized range in cell or other declaration");
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"Unsupported or syntax error: Unsized range in instance or other declaration");
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nodep->unlinkFrBack();
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VL_DO_DANGLING(nodep->deleteTree(), nodep);
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}
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}
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if (nrangep && nrangep->nextp()) {
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// Not supported by at least 2 of big 3
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nrangep->nextp()->v3warn(E_UNSUPPORTED, "Unsupported: Multidimensional cells/interfaces.");
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nrangep->nextp()->v3warn(E_UNSUPPORTED,
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"Unsupported: Multidimensional instances/interfaces.");
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nrangep->nextp()->unlinkFrBackWithNext()->deleteTree();
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}
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return VN_CAST(nrangep, Range);
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@ -267,7 +267,7 @@ public:
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scopes += AstNode::prettyName(it->first);
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}
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}
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if (scopes == "") scopes = "<no cells found>";
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if (scopes == "") scopes = "<no instances found>";
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std::cerr << V3Error::warnMore() << "... Known scopes under '" << prettyName
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<< "': " << scopes << endl;
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if (debug()) dump(std::cerr, " KnownScope: ", 1);
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@ -59,7 +59,7 @@ private:
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if (!varp->isTrace()) {
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return "Verilator trace_off";
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} else if (!nodep->isTrace()) {
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return "Verilator cell trace_off";
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return "Verilator instance trace_off";
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} else if (!v3Global.opt.traceUnderscore()) {
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const string prettyName = varp->prettyName();
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if (!prettyName.empty() && prettyName[0] == '_') return "Leading underscore";
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@ -1,2 +1,2 @@
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%Error: Specified --top-module 'a' isn't at the top level, it's under another cell 'a_top'
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%Error: Specified --top-module 'a' isn't at the top level, it's under another instance 'a_top'
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%Error: Exiting due to
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@ -1,17 +1,17 @@
|
||||
%Warning-LITENDIAN: t/t_interface_array_nocolon_bad.v:26:26: Little endian cell range connecting to vector: left < right of cell range: [0:2]
|
||||
%Warning-LITENDIAN: t/t_interface_array_nocolon_bad.v:26:26: Little endian instance range connecting to vector: left < right of instance range: [0:2]
|
||||
: ... In instance t
|
||||
26 | foo_intf foos [N] (.x(X));
|
||||
| ^
|
||||
... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.
|
||||
%Warning-LITENDIAN: t/t_interface_array_nocolon_bad.v:27:28: Little endian cell range connecting to vector: left < right of cell range: [1:3]
|
||||
%Warning-LITENDIAN: t/t_interface_array_nocolon_bad.v:27:28: Little endian instance range connecting to vector: left < right of instance range: [1:3]
|
||||
: ... In instance t
|
||||
27 | foo_intf fool [1:3] (.x(X));
|
||||
| ^
|
||||
%Warning-LITENDIAN: t/t_interface_array_nocolon_bad.v:30:26: Little endian cell range connecting to vector: left < right of cell range: [0:2]
|
||||
%Warning-LITENDIAN: t/t_interface_array_nocolon_bad.v:30:26: Little endian instance range connecting to vector: left < right of instance range: [0:2]
|
||||
: ... In instance t
|
||||
30 | foo_subm subs [N] (.x(X));
|
||||
| ^
|
||||
%Warning-LITENDIAN: t/t_interface_array_nocolon_bad.v:31:28: Little endian cell range connecting to vector: left < right of cell range: [1:3]
|
||||
%Warning-LITENDIAN: t/t_interface_array_nocolon_bad.v:31:28: Little endian instance range connecting to vector: left < right of instance range: [1:3]
|
||||
: ... In instance t
|
||||
31 | foo_subm subl [1:3] (.x(X));
|
||||
| ^
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
%Error: t/t_interface_mismodport_bad.v:36:12: Can't find definition of 'bad' in dotted signal: 'isub.bad'
|
||||
36 | isub.bad = i_value;
|
||||
| ^~~
|
||||
... Known scopes under 'bad': <no cells found>
|
||||
... Known scopes under 'bad': <no instances found>
|
||||
%Error: Exiting due to
|
||||
|
||||
@ -1,7 +1,7 @@
|
||||
%Error-UNSUPPORTED: t/t_interface_top_bad.v:17:19: Unsupported: Interfaced port on top level module
|
||||
17 | ifc.counter_mp c_data
|
||||
| ^~~~~~
|
||||
%Error: t/t_interface_top_bad.v:17:4: Parent cell's interface is not found: 'ifc'
|
||||
%Error: t/t_interface_top_bad.v:17:4: Parent instance's interface is not found: 'ifc'
|
||||
17 | ifc.counter_mp c_data
|
||||
| ^~~
|
||||
%Error: Exiting due to
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
%Error: t/t_interface_typo_bad.v:14:4: Parent cell's interface is not found: 'foo_intf'
|
||||
%Error: t/t_interface_typo_bad.v:14:4: Parent instance's interface is not found: 'foo_intf'
|
||||
14 | foo_intf foo
|
||||
| ^~~~~~~~
|
||||
%Error: t/t_interface_typo_bad.v:22:4: Cannot find file containing interface: 'fo_intf'
|
||||
|
||||
@ -1,7 +1,7 @@
|
||||
%Error-UNSUPPORTED: t/t_mod_interface_array3.v:25:20: Unsupported: Multidimensional cells/interfaces.
|
||||
%Error-UNSUPPORTED: t/t_mod_interface_array3.v:25:20: Unsupported: Multidimensional instances/interfaces.
|
||||
25 | a_if iface [2:0][1:0];
|
||||
| ^
|
||||
%Error-UNSUPPORTED: t/t_mod_interface_array3.v:27:18: Unsupported: Multidimensional cells/interfaces.
|
||||
%Error-UNSUPPORTED: t/t_mod_interface_array3.v:27:18: Unsupported: Multidimensional instances/interfaces.
|
||||
27 | sub i_sub[2:0][1:0] (.s(str));
|
||||
| ^
|
||||
%Error: Exiting due to
|
||||
|
||||
@ -1,19 +1,19 @@
|
||||
%Error: t/t_var_bad_sameas.v:10:8: Unsupported in C: Cell has the same name as variable: 'varfirst'
|
||||
%Error: t/t_var_bad_sameas.v:10:8: Unsupported in C: Instance has the same name as variable: 'varfirst'
|
||||
10 | sub varfirst ();
|
||||
| ^~~~~~~~
|
||||
t/t_var_bad_sameas.v:9:12: ... Location of original declaration
|
||||
9 | integer varfirst;
|
||||
| ^~~~~~~~
|
||||
%Error: t/t_var_bad_sameas.v:11:9: Unsupported in C: Task has the same name as cell: 'varfirst'
|
||||
%Error: t/t_var_bad_sameas.v:11:9: Unsupported in C: Task has the same name as instance: 'varfirst'
|
||||
11 | task varfirst; begin end endtask
|
||||
| ^~~~~~~~
|
||||
t/t_var_bad_sameas.v:10:8: ... Location of original declaration
|
||||
10 | sub varfirst ();
|
||||
| ^~~~~~~~
|
||||
%Error: t/t_var_bad_sameas.v:14:12: Unsupported in C: Variable has same name as cell: 'cellfirst'
|
||||
%Error: t/t_var_bad_sameas.v:14:12: Unsupported in C: Variable has same name as instance: 'cellfirst'
|
||||
14 | integer cellfirst;
|
||||
| ^~~~~~~~~
|
||||
%Error: t/t_var_bad_sameas.v:15:9: Unsupported in C: Task has the same name as cell: 'cellfirst'
|
||||
%Error: t/t_var_bad_sameas.v:15:9: Unsupported in C: Task has the same name as instance: 'cellfirst'
|
||||
15 | task cellfirst; begin end endtask
|
||||
| ^~~~~~~~~
|
||||
t/t_var_bad_sameas.v:13:8: ... Location of original declaration
|
||||
@ -22,7 +22,7 @@
|
||||
%Error: t/t_var_bad_sameas.v:18:12: Unsupported in C: Variable has same name as task: 'taskfirst'
|
||||
18 | integer taskfirst;
|
||||
| ^~~~~~~~~
|
||||
%Error: t/t_var_bad_sameas.v:19:8: Unsupported in C: Cell has the same name as task: 'taskfirst'
|
||||
%Error: t/t_var_bad_sameas.v:19:8: Unsupported in C: Instance has the same name as task: 'taskfirst'
|
||||
19 | sub taskfirst ();
|
||||
| ^~~~~~~~~
|
||||
t/t_var_bad_sameas.v:17:9: ... Location of original declaration
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
%Error: t/t_var_dotted_dup_bad.v:14:18: Duplicate declaration of cell: 'dccm_bank'
|
||||
%Error: t/t_var_dotted_dup_bad.v:14:18: Duplicate declaration of instance: 'dccm_bank'
|
||||
14 | eh2_ram dccm_bank (.*);
|
||||
| ^~~~~~~~~
|
||||
t/t_var_dotted_dup_bad.v:11:18: ... Location of original declaration
|
||||
|
||||
Loading…
Reference in New Issue
Block a user