From 94c8064798901b1b658552564e4a8d9a378bbfed Mon Sep 17 00:00:00 2001 From: John Coiner Date: Thu, 7 Jun 2018 12:43:19 -0400 Subject: [PATCH 1/2] Fix linear search; this is part of the fix for issue 1316. --- src/V3Delayed.cpp | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/V3Delayed.cpp b/src/V3Delayed.cpp index 9ea69f258..91c17134e 100644 --- a/src/V3Delayed.cpp +++ b/src/V3Delayed.cpp @@ -150,7 +150,8 @@ private: AstActive* createActivePost(AstVarRef* varrefp) { AstActive* newactp = new AstActive (varrefp->fileline(), "sequentdly", m_activep->sensesp()); - m_activep->addNext(newactp); + // Was addNext(), but addNextHere() avoids a linear search. + m_activep->addNextHere(newactp); return newactp; } void checkActivePost(AstVarRef* varrefp, AstActive* oldactivep) { From f0ed4346b2e13aa8ae51566dae587d3af0bf4ea9 Mon Sep 17 00:00:00 2001 From: James Hutchinson Date: Fri, 8 Jun 2018 08:01:22 -0400 Subject: [PATCH 2/2] Fix to be in verilog 2005, bug1319. Signed-off-by: Wilson Snyder --- Changes | 2 ++ src/verilog.l | 3 ++- 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/Changes b/Changes index 9b30db056..75b1843de 100644 --- a/Changes +++ b/Changes @@ -14,6 +14,8 @@ The contributors that suggested a given feature are shown in []. Thanks! **** Fix parsing error on bad missing #, bug1308. [Dan Kirkham] +**** Fix $clog2 to be in verilog 2005, bug1319. [James Hutchinson] + * Verilator 3.922 2018-03-17 diff --git a/src/verilog.l b/src/verilog.l index 5702b7461..bb20c9d3f 100644 --- a/src/verilog.l +++ b/src/verilog.l @@ -422,6 +422,8 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5} /* Verilog 2005 */ { + /* System Tasks */ + "$clog2" { FL; return yD_CLOG2; } /* Keywords */ "uwire" { FL; return yWIRE; } } @@ -430,7 +432,6 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5} { /* System Tasks */ "$bits" { FL; return yD_BITS; } - "$clog2" { FL; return yD_CLOG2; } "$countones" { FL; return yD_COUNTONES; } "$dimensions" { FL; return yD_DIMENSIONS; } "$error" { FL; return yD_ERROR; }