diff --git a/Changes b/Changes index 61742c76f..74722c4d0 100644 --- a/Changes +++ b/Changes @@ -5,6 +5,8 @@ The contributors that suggested a given feature are shown in []. Thanks! * Verilator 3.901 devel +**** Fix 2009 localparam syntax, msg2139. [Galen Seitz] + * Verilator 3.900 2017-01-15 diff --git a/src/verilog.y b/src/verilog.y index 57923083c..a7750a909 100644 --- a/src/verilog.y +++ b/src/verilog.y @@ -1155,10 +1155,14 @@ parameter_declarationFront: // IEEE: parameter_declaration w/o assignment parameter_port_declarationFrontE: // IEEE: parameter_port_declaration w/o assignment // // IEEE: parameter_declaration (minus assignment) + // // IEEE: local_parameter_declaration (minus assignment) // // Front must execute first so VARDTYPE is ready before list of vars varGParamReset implicit_typeE { /*VARRESET-in-varGParam*/ VARDTYPE($2); } | varGParamReset data_type { /*VARRESET-in-varGParam*/ VARDTYPE($2); } | varGParamReset yTYPE { /*VARRESET-in-varGParam*/ VARDTYPE(new AstParseTypeDType($2)); } + | varLParamReset implicit_typeE { /*VARRESET-in-varLParam*/ VARDTYPE($2); } + | varLParamReset data_type { /*VARRESET-in-varLParam*/ VARDTYPE($2); } + | varLParamReset yTYPE { /*VARRESET-in-varLParam*/ VARDTYPE(new AstParseTypeDType($2)); } | implicit_typeE { /*VARRESET-in-varGParam*/ VARDTYPE($1); } | data_type { /*VARRESET-in-varGParam*/ VARDTYPE($1); } | yTYPE { /*VARRESET-in-varGParam*/ VARDTYPE(new AstParseTypeDType($1)); } diff --git a/test_regress/t/t_param_local.pl b/test_regress/t/t_param_local.pl new file mode 100755 index 000000000..f91289753 --- /dev/null +++ b/test_regress/t/t_param_local.pl @@ -0,0 +1,18 @@ +#!/usr/bin/perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. + +compile ( + ); + +execute ( + check_finished=>1, + ); + +ok(1); +1; diff --git a/test_regress/t/t_param_local.v b/test_regress/t/t_param_local.v new file mode 100644 index 000000000..a500bf9b1 --- /dev/null +++ b/test_regress/t/t_param_local.v @@ -0,0 +1,28 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2017 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + a, y + ); + + input [1:0] a; + output [3:0] y; + + Test #(.C(2)) + test (.*); +endmodule + +module Test + #(C = 3, + localparam O = 1 << C) + (input [C-1:0] a, + output reg [O-1:0] y); + initial begin + if (O != 4) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule