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Tests: Add -G test.
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test_regress/t/t_flag_parameter_hier.pl
Executable file
33
test_regress/t/t_flag_parameter_hier.pl
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#!/usr/bin/perl
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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2008 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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scenarios(simulator => 1);
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compile(
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# For Verilator, all PARAMs at all levels are overwridden
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# Error if parameter not found
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#verilator_flags2 => ['-GPARAM=10 -Gtop.t.x.HIER=20'], # HIER would error
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verilator_flags2 => ['-GPARAM=10'],
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# For NC, always implies a hierarchy, only HIER will be set
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# Warns if sets nothing
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nc_flags2 => ['+defparam+PARAM=10 +defparam+top.t.x.HIER=20'],
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# For VCS, all PARAMs at all levels are overridden. Hierarchy not allowed.
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# Informational on all overrides
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vcs_flags2 => ['-pvalue+PARAM=10 -px.HIER=20'],
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# For icarus -P without hierarchy does nothing, only can ref into top
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iv_flags2 => ['-PPARAM=10', '-Ptop.HIER=30', '-Ptop.t.x.HIER=20'],
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);
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execute(
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check_finished => 1,
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);
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ok(1);
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1;
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83
test_regress/t/t_flag_parameter_hier.v
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83
test_regress/t/t_flag_parameter_hier.v
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2016 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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`define check(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: %m: Wrong parameter value\n", `__FILE__,`__LINE__); $stop; end while(0);
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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u u ();
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tx x ();
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parameter PARAM = 0;
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parameter HIER = 0;
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initial begin
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$display("%m PARAM=%0d HIER=%0d", PARAM, HIER);
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`ifdef IVERILOG
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`check(PARAM, 0);
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`elsif NC
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`check(PARAM, 0);
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`elsif VCS
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`check(PARAM, 10);
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`else
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`check(PARAM, 10);
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`endif
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`check(HIER, 0);
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end
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always @ (posedge clk) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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module u;
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ux x();
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endmodule
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module ux;
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parameter PARAM = 0;
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parameter HIER = 0;
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initial begin
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$display("%m PARAM=%0d HIER=%0d", PARAM, HIER);
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`ifdef IVERILOG
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`check(PARAM, 0);
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`elsif NC
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`check(PARAM, 0);
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`elsif VCS
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`check(PARAM, 10);
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`else
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`check(PARAM, 0);
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`endif
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`check(HIER, 0);
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end
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endmodule
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module tx;
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parameter PARAM = 0;
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parameter HIER = 0;
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initial begin
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$display("%m PARAM=%0d HIER=%0d", PARAM, HIER);
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`ifdef IVERILOG
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`check(PARAM, 0);
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`elsif NC
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`check(PARAM, 10);
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`elsif VCS
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`check(PARAM, 10);
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`else
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`check(PARAM, 0);
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`endif
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`ifdef NC
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`check(HIER, 20);
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`else
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`check(HIER, 0);
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`endif
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end
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endmodule
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