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synced 2025-04-16 01:26:54 +00:00
Support inside operator on unpacked arrays and queues (#4751)
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@ -613,6 +613,11 @@ public:
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m_deque.insert(m_deque.begin() + index, value);
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}
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// inside (set membership operator)
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bool inside(const T_Value& value) const {
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return std::find(m_deque.begin(), m_deque.end(), value) != m_deque.end();
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}
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// Return slice q[lsb:msb]
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VlQueue slice(int32_t lsb, int32_t msb) const {
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VlQueue out;
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@ -1308,6 +1313,11 @@ public:
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bool operator==(const VlUnpacked<T_Value, T_Depth>& that) const { return !neq(that); }
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bool operator!=(const VlUnpacked<T_Value, T_Depth>& that) { return neq(that); }
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// inside (set membership operator)
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bool inside(const T_Value& value) const {
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return std::find(std::begin(m_storage), std::end(m_storage), value) != std::end(m_storage);
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}
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void sort() { std::sort(std::begin(m_storage), std::end(m_storage)); }
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template <typename Func>
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void sort(Func with_func) {
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@ -2252,6 +2252,7 @@ void AstCMethodHard::setPurity() {
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{"first", false},
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{"init", false},
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{"insert", false},
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{"inside", true},
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{"isFired", true},
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{"isTriggered", true},
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{"join", false},
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@ -2555,16 +2555,16 @@ class WidthVisitor final : public VNVisitor {
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// Similar logic in V3Case
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inewp = irangep->newAndFromInside(nodep->exprp(), irangep->lhsp()->unlinkFrBack(),
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irangep->rhsp()->unlinkFrBack());
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} else if (VN_IS(itemDtp, UnpackArrayDType)) {
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nodep->v3error("Unsupported: inside (set membership operator) on unpacked array");
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// Need the AstInside type to persist, then
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// for parameters, need V3Simulate support.
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// For non-parameters, need runtime support.
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continue;
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} else if (VN_IS(itemDtp, AssocArrayDType) || VN_IS(itemDtp, DynArrayDType)
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} else if (VN_IS(itemDtp, UnpackArrayDType) || VN_IS(itemDtp, DynArrayDType)
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|| VN_IS(itemDtp, QueueDType)) {
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nodep->v3error(
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"Inside operator not legal on non-unpacked arrays (IEEE 1800-2017 11.4.13)");
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// Unsupported in parameters
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inewp = new AstCMethodHard{itemp->fileline(), itemp->unlinkFrBack(), "inside",
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nodep->exprp()->cloneTreePure(true)};
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inewp->dtypeSetBit();
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inewp->didWidth(true);
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} else if (VN_IS(itemDtp, AssocArrayDType)) {
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nodep->v3error("Inside operator not specified on associative arrays (IEEE "
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"1800-2017 11.4.13)");
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continue;
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} else {
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inewp = AstEqWild::newTyped(itemp->fileline(), nodep->exprp()->cloneTreePure(true),
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5
test_regress/t/t_inside_assoc_unsup.out
Normal file
5
test_regress/t/t_inside_assoc_unsup.out
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@ -0,0 +1,5 @@
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%Error: t/t_inside_assoc_unsup.v:12:15: Inside operator not specified on associative arrays (IEEE 1800-2017 11.4.13)
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: ... note: In instance 't'
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12 | m = (10 inside {assoc});
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| ^~~~~~
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%Error: Exiting due to
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@ -5,16 +5,11 @@
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// SPDX-License-Identifier: CC0-1.0
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module t(/*AUTOARG*/);
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int q[$];
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int assoc[int];
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int dyn[];
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bit m;
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initial begin
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m = (10 inside {q});
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m = (10 inside {assoc});
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m = (10 inside {dyn});
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end
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endmodule
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21
test_regress/t/t_inside_dyn.pl
Executable file
21
test_regress/t/t_inside_dyn.pl
Executable file
@ -0,0 +1,21 @@
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#!/usr/bin/env perl
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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2022 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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scenarios(simulator => 1);
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compile(
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);
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execute(
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check_finished => 1,
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);
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ok(1);
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1;
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22
test_regress/t/t_inside_dyn.v
Normal file
22
test_regress/t/t_inside_dyn.v
Normal file
@ -0,0 +1,22 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2023 by Antmicro Ltd.
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// SPDX-License-Identifier: CC0-1.0
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module t;
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int q[$] = '{1, 2, 3};
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bit dyn[] = '{0, 0};
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initial begin
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if (!(1 inside {q})) $stop;
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if (4 inside {q}) $stop;
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if (!(4 inside {q, 4})) $stop;
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if (!(0 inside {dyn})) $stop;
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if (1 inside {dyn}) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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@ -1,13 +0,0 @@
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%Error: t/t_inside_queue_bad.v:15:15: Inside operator not legal on non-unpacked arrays (IEEE 1800-2017 11.4.13)
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: ... note: In instance 't'
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15 | m = (10 inside {q});
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| ^~~~~~
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%Error: t/t_inside_queue_bad.v:16:15: Inside operator not legal on non-unpacked arrays (IEEE 1800-2017 11.4.13)
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: ... note: In instance 't'
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16 | m = (10 inside {assoc});
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| ^~~~~~
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%Error: t/t_inside_queue_bad.v:17:15: Inside operator not legal on non-unpacked arrays (IEEE 1800-2017 11.4.13)
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: ... note: In instance 't'
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17 | m = (10 inside {dyn});
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| ^~~~~~
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%Error: Exiting due to
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@ -11,13 +11,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
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scenarios(simulator => 1);
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compile(
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fails => $Self->{vlt_all},
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expect_filename => $Self->{golden_filename},
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);
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execute(
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check_finished => 1,
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) if !$Self->{vlt_all};
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);
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ok(1);
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1;
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@ -10,18 +10,6 @@ module t(/*AUTOARG*/
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);
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input clk;
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localparam int CHECKLIST_P [2:0] = '{0, 1, 2};
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localparam HIT_LP = 1;
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localparam MISS_LP = 4;
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localparam HIT_INSIDE = HIT_LP inside {CHECKLIST_P};
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localparam MISS_INSIDE = MISS_LP inside {CHECKLIST_P};
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initial begin
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if (HIT_INSIDE != 1) $stop;
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if (MISS_INSIDE != 0) $stop;
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end
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integer cyc = 0;
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int array [10];
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9
test_regress/t/t_inside_unpacked_param.out
Normal file
9
test_regress/t/t_inside_unpacked_param.out
Normal file
@ -0,0 +1,9 @@
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%Error: t/t_inside_unpacked_param.v:13:43: Expecting expression to be constant, but can't convert a CMETHODHARD 'inside' to constant.
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: ... note: In instance 't'
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13 | localparam HIT_INSIDE = HIT_LP inside {CHECKLIST_P};
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| ^~~~~~~~~~~
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%Error: t/t_inside_unpacked_param.v:14:45: Expecting expression to be constant, but can't convert a CMETHODHARD 'inside' to constant.
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: ... note: In instance 't'
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14 | localparam MISS_INSIDE = MISS_LP inside {CHECKLIST_P};
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| ^~~~~~~~~~~
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%Error: Exiting due to
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23
test_regress/t/t_inside_unpacked_param.pl
Executable file
23
test_regress/t/t_inside_unpacked_param.pl
Executable file
@ -0,0 +1,23 @@
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#!/usr/bin/env perl
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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2019 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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scenarios(simulator => 1);
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compile(
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fails => $Self->{vlt_all},
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expect_filename => $Self->{golden_filename},
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);
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execute(
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check_finished => 1,
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) if !$Self->{vlt_all};
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ok(1);
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1;
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22
test_regress/t/t_inside_unpacked_param.v
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22
test_regress/t/t_inside_unpacked_param.v
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@ -0,0 +1,22 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2020 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t;
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localparam int CHECKLIST_P [2:0] = '{0, 1, 2};
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localparam HIT_LP = 1;
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localparam MISS_LP = 4;
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localparam HIT_INSIDE = HIT_LP inside {CHECKLIST_P};
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localparam MISS_INSIDE = MISS_LP inside {CHECKLIST_P};
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initial begin
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if (HIT_INSIDE != 1) $stop;
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if (MISS_INSIDE != 0) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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