From a6ad85244fe3ccba4a0c57d80d62c7dabbb4cd17 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Sun, 4 Feb 2024 18:13:22 -0500 Subject: [PATCH] Backout (#4710) due to leak --- Changes | 1 - src/V3LinkDot.cpp | 4 ++-- test_regress/t/t_0.pl | 21 --------------------- test_regress/t/t_0.v | 37 ------------------------------------- 4 files changed, 2 insertions(+), 61 deletions(-) delete mode 100755 test_regress/t/t_0.pl delete mode 100644 test_regress/t/t_0.v diff --git a/Changes b/Changes index a8bddc209..95f7afa2e 100644 --- a/Changes +++ b/Changes @@ -25,7 +25,6 @@ Verilator 5.021 devel * Support SystemC 3.0.0 public review version (#4805) (#4807). [Anthony Donlon] * Support parsing anonymous primitive instantiations (#4809). [Anthony Donlon] * Fix to not emit already waived warnings in waiver output (#4574) (#4818). [Jonathan Schröter] -* Fix `this` in member initialization (#4710). [eliasphanna] * Fix localparam elaboration (#3858) (#4794). [Andrew Nolte] * Fix lint_off disables on preprocessor warnings (#4703). [Srinivasan Venkataramanan] * Fix $time not rounding up (#4790) (#4792). [Paul Wright] diff --git a/src/V3LinkDot.cpp b/src/V3LinkDot.cpp index f6eb6fe06..a8f6a58a7 100644 --- a/src/V3LinkDot.cpp +++ b/src/V3LinkDot.cpp @@ -2208,9 +2208,9 @@ class LinkDotResolveVisitor final : public VNVisitor { } VSymEnt* getThisClassSymp() { VSymEnt* classSymp = m_ds.m_dotSymp; - while (classSymp && !VN_IS(classSymp->nodep(), Class)) { + do { classSymp = classSymp->parentp(); - } + } while (classSymp && !VN_IS(classSymp->nodep(), Class)); return classSymp; } void importImplementsClass(AstClass* implementsClassp, VSymEnt* interfaceSymp, diff --git a/test_regress/t/t_0.pl b/test_regress/t/t_0.pl deleted file mode 100755 index e64ab41be..000000000 --- a/test_regress/t/t_0.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -scenarios(simulator => 1); - -compile( - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_0.v b/test_regress/t/t_0.v deleted file mode 100644 index 81a33cba0..000000000 --- a/test_regress/t/t_0.v +++ /dev/null @@ -1,37 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -interface class ICls; - pure virtual function string get(); -endclass - -class Cls; - string name; - ICls icls; - function new(string name, ICls icls); - this.name = name; - this.icls = icls; - endfunction -endclass - -class Testcase implements ICls; - Cls cls = new("test_class", this); - virtual function string get(); - return "In ICls"; - endfunction -endclass - -module t(/*AUTOARG*/); - - initial begin - Testcase test; - test = new; - if (test.cls.name != "test_class") $stop; - if (test.cls.icls.get() != "In ICls") $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - -endmodule