Tests: Avoid verilated.v include in most tests

src/V3Tristate.cpp

@@ -710,6 +710,12 @@ class TristateVisitor final : public TristateBaseVisitor {
         ++m_statTriSigs;
         m_tgraph.didProcess(invarp);
 
+        const AstBasicDType* const basicp = VN_CAST(invarp->dtypep()->skipRefp(), BasicDType);
+        if (!basicp || basicp->isOpaque())
+            invarp->v3warn(E_UNSUPPORTED,
+                           "Unsupported: Inout/tristate with non-bit/logic data type: "
+                               << invarp->dtypep()->prettyTypeName());
+
         // If the lhs var is a port, then we need to create ports for
         // the output (__out) and output enable (__en) signals. The
         // original port gets converted to an input. Don't tristate expand

test_regress/input.vc

@@ -2,4 +2,3 @@
 +librescan +notimingchecks +libext+.v
  -y t
  +incdir+t
- +incdir+../include

test_regress/input.xsim.vc

@@ -3,5 +3,4 @@
  --sourcelibdir t
  --sourcelibdir obj_dir/
  --include t
- --include ../include
  --include obj_dir/

test_regress/t/t_case_write1.v

@@ -4,8 +4,6 @@
 // any use, without warranty, 2006 by Wilson Snyder.
 // SPDX-License-Identifier: CC0-1.0
 
-`include "verilated.v"
-
 `define STRINGIFY(x) `"x`"
 
 module t (/*AUTOARG*/

test_regress/t/t_case_write1_tasks.v

@@ -4,8 +4,6 @@
 // any use, without warranty, 2006 by Wilson Snyder.
 // SPDX-License-Identifier: CC0-1.0
 
-`include "verilated.v"
-
 module t_case_write1_tasks ();
 
    // verilator lint_off WIDTH

test_regress/t/t_case_write2.v

@@ -4,8 +4,6 @@
 // any use, without warranty, 2006 by Wilson Snyder.
 // SPDX-License-Identifier: CC0-1.0
 
-`include "verilated.v"
-
 `define STRINGIFY(x) `"x`"
 
 module t (/*AUTOARG*/

test_regress/t/t_case_write2_tasks.v

@@ -4,8 +4,6 @@
 // any use, without warranty, 2006 by Wilson Snyder.
 // SPDX-License-Identifier: CC0-1.0
 
-`include "verilated.v"
-
 module t_case_write2_tasks ();
 
    // verilator lint_off WIDTH

test_regress/t/t_gen_missing_bad.out

@@ -5,9 +5,6 @@
              t/foo_not_needed
              t/foo_not_needed.v
              t/foo_not_needed.sv
-             ../include/foo_not_needed
-             ../include/foo_not_needed.v
-             ../include/foo_not_needed.sv
              foo_not_needed
              foo_not_needed.v
              foo_not_needed.sv

test_regress/t/t_preproc_inc_notfound_bad.out

@@ -5,9 +5,6 @@
              t/this_file_is_not_found.vh
              t/this_file_is_not_found.vh.v
              t/this_file_is_not_found.vh.sv
-             ../include/this_file_is_not_found.vh
-             ../include/this_file_is_not_found.vh.v
-             ../include/this_file_is_not_found.vh.sv
              this_file_is_not_found.vh
              this_file_is_not_found.vh.v
              this_file_is_not_found.vh.sv

test_regress/t/t_sys_file_basic.v

@@ -4,8 +4,6 @@
 // any use, without warranty, 2003 by Wilson Snyder.
 // SPDX-License-Identifier: CC0-1.0
 
-`include "verilated.v"
-
 `define STRINGIFY(x) `"x`"
 `define ratio_error(a,b) (((a)>(b) ? ((a)-(b)) : ((b)-(a))) /(a))
 `define stop $stop

test_regress/t/t_sys_file_eof.v

@@ -4,8 +4,6 @@
 // any use, without warranty, 2022 by Wilson Snyder.
 // SPDX-License-Identifier: CC0-1.0
 
-`include "verilated.v"
-
 `define stop $stop
 `define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
 

test_regress/t/t_sys_file_scan.v

@@ -4,8 +4,6 @@
 // any use, without warranty, 2008 by Wilson Snyder.
 // SPDX-License-Identifier: CC0-1.0
 
-`include "verilated.v"
-
 `define STRINGIFY(x) `"x`"
 
 module t;

test_regress/t/t_sys_sformat.v

@@ -4,8 +4,6 @@
 // any use, without warranty, 2008 by Wilson Snyder.
 // SPDX-License-Identifier: CC0-1.0
 
-`include "verilated.v"
-
 module t;
 
    // Note $sscanf already tested elsewhere

test_regress/t/t_tri_array.out

@@ -7,6 +7,10 @@
                                          : ... note: In instance 't'
    28 |       Pad pad0 (.pad(pad[g]),
       |                         ^
+%Error-UNSUPPORTED: t/t_tri_array.v:19:17: Unsupported: Inout/tristate with non-bit/logic data type: UNPACKARRAYDTYPE
+                                         : ... note: In instance 't'
+   19 |    tri          pad [NPAD-1:0];   
+      |                 ^~~
 %Error: t/t_tri_array.v:25:25: Select from non-array BASICDTYPE 'bit'
                              : ... note: In instance 't'
    25 |       Pad pad1 (.pad(pad[g]),

test_regress/t/t_tri_array.pl

@@ -8,7 +8,7 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 # Version 2.0.
 # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
-scenarios(simulator => 1);
+scenarios(simulator_st => 1);
 
 compile(
     fails => $Self->{vlt_all},

test_regress/t/t_tri_struct.out

@@ -0,0 +1,34 @@
+%Error-UNSUPPORTED: t/t_tri_struct.v:20:31: Unsupported: Inout/tristate with non-bit/logic data type: REFDTYPE 'u_struct_t'
+                                          : ... note: In instance 't.u_mh'
+   20 | module u_mh (inout u_struct_t u_i, inout u_struct_t u_o);
+      |                               ^~~
+                    ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
+%Error-UNSUPPORTED: t/t_tri_struct.v:20:53: Unsupported: Inout/tristate with non-bit/logic data type: REFDTYPE 'u_struct_t'
+                                          : ... note: In instance 't.u_mh'
+   20 | module u_mh (inout u_struct_t u_i, inout u_struct_t u_o);
+      |                                                     ^~~
+%Error-UNSUPPORTED: t/t_tri_struct.v:15:31: Unsupported: Inout/tristate with non-bit/logic data type: REFDTYPE 'p_struct_t'
+                                          : ... note: In instance 't.p_mh'
+   15 | module p_mh (inout p_struct_t p_i, inout p_struct_t p_o);
+      |                               ^~~
+%Error-UNSUPPORTED: t/t_tri_struct.v:15:53: Unsupported: Inout/tristate with non-bit/logic data type: REFDTYPE 'p_struct_t'
+                                          : ... note: In instance 't.p_mh'
+   15 | module p_mh (inout p_struct_t p_i, inout p_struct_t p_o);
+      |                                                     ^~~
+%Error-UNSUPPORTED: t/t_tri_struct.v:26:15: Unsupported: Inout/tristate with non-bit/logic data type: REFDTYPE 'p_struct_t'
+                                          : ... note: In instance 't'
+   26 |    p_struct_t p_i, p_o;
+      |               ^~~
+%Error-UNSUPPORTED: t/t_tri_struct.v:26:20: Unsupported: Inout/tristate with non-bit/logic data type: REFDTYPE 'p_struct_t'
+                                          : ... note: In instance 't'
+   26 |    p_struct_t p_i, p_o;
+      |                    ^~~
+%Error-UNSUPPORTED: t/t_tri_struct.v:27:15: Unsupported: Inout/tristate with non-bit/logic data type: REFDTYPE 'u_struct_t'
+                                          : ... note: In instance 't'
+   27 |    u_struct_t u_i, u_o;
+      |               ^~~
+%Error-UNSUPPORTED: t/t_tri_struct.v:27:20: Unsupported: Inout/tristate with non-bit/logic data type: REFDTYPE 'u_struct_t'
+                                          : ... note: In instance 't'
+   27 |    u_struct_t u_i, u_o;
+      |                    ^~~
+%Error: Exiting due to

test_regress/t/t_tri_struct.pl

@@ -0,0 +1,24 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(simulator_st => 1);
+
+compile(
+    verilator_flags2 => ['--exe --main --timing'],
+    fails => $Self->{vlt_all},
+    expect_filename => $Self->{golden_filename},
+    );
+
+execute(
+    check_finished => 1,
+    ) if !$Self->{vlt};
+
+ok(1);
+1;

test_regress/t/t_tri_struct.v

@@ -0,0 +1,41 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2024 by Ryszard Rozak.
+// SPDX-License-Identifier: CC0-1.0
+
+typedef struct packed {
+   bit x;
+} p_struct_t;
+
+typedef struct {
+   bit x;
+} u_struct_t;
+
+module p_mh (inout p_struct_t p_i, inout p_struct_t p_o);
+   // OK: module p_mh (input p_struct_t p_i, output p_struct_t p_o);
+   assign p_o.x = p_i.x;
+endmodule
+
+module u_mh (inout u_struct_t u_i, inout u_struct_t u_o);
+   // OK: module u_mh (input u_struct_t u_i, output u_struct_t u_o);
+   assign u_o.x = u_i.x;
+endmodule
+
+module t;
+   p_struct_t p_i, p_o;
+   u_struct_t u_i, u_o;
+
+   p_mh p_mh(p_i, p_o);
+   u_mh u_mh(u_i, u_o);
+
+   initial begin
+      p_i.x = 1;
+      u_i.x = 1;
+      #1;
+      if (p_o.x != 1'b1) $stop;
+      if (u_o.x != 1'b1) $stop;
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+endmodule

test_regress/t/t_verilated_header.pl

@@ -0,0 +1,22 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(simulator_st => 1);
+
+compile(
+    verilator_flags2 => ['+incdir+../include'],
+    );
+
+execute(
+    check_finished => 1,
+    );
+
+ok(1);
+1;

test_regress/t/t_verilated_header.v

@@ -0,0 +1,19 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2023 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+`include "verilated.v"
+
+module t (/*AUTOARG*/);
+
+   initial begin
+      `verilator_file_descriptor i;
+      `coverage_block_off
+      i = $fopen("/dev/null", "r");
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+
+endmodule