github/verilator
1
0
Fork 1
mirror of https://github.com/verilator/verilator.git synced 2025-01-01 04:07:34 +00:00
Code Issues Packages Projects Releases Wiki Activity

Spelling fixes

Browse Source 
Signed-off-by: Wilson Snyder <wsnyder@wsnyder.org>
This commit is contained in:
Ahmed El-Mahmoudy 2017-10-16 21:57:55 -04:00 committed by Wilson Snyder
parent f5dfa1e9c3
commit a69936de74
2 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
bin/verilator
View File

@ -2349,7 +2349,7 @@ Verilator configuration commands.
Switch back to processing Verilog code after a `systemc_... mode switch.
The Verilog code returns to the last language mode specified with
`begin_keywords, or SystemVerilog if none were specified.
`begin_keywords, or SystemVerilog if none was specified.
=item /*verilator clock_enable*/

2
src/V3StatsReport.cpp
View File

@ -102,7 +102,7 @@ class StatsReport {
os<<endl;
// Print organized by stage
os<<"Peformance Statistics:\n";
os<<"Performance Statistics:\n";
os<<endl;
for (ByName::iterator it = byName.begin(); it!=byName.end(); ++it) {
const V3Statistic* repp = it->second;