From a3c154dcd3fb0ec4768eaa3be2c3dd7b648376b3 Mon Sep 17 00:00:00 2001
From: Ryszard Rozak <rrozak@antmicro.com>
Date: Tue, 3 Oct 2023 14:32:18 +0200
Subject: [PATCH] Fix this in a constructor (#4533)

---
 include/verilated_types.h                  |  5 +++--
 test_regress/t/t_class_this_constructor.pl | 21 +++++++++++++++++
 test_regress/t/t_class_this_constructor.v  | 26 ++++++++++++++++++++++
 3 files changed, 50 insertions(+), 2 deletions(-)
 create mode 100755 test_regress/t/t_class_this_constructor.pl
 create mode 100644 test_regress/t/t_class_this_constructor.v

diff --git a/include/verilated_types.h b/include/verilated_types.h
index 6a1a3bfac..cb40b0e82 100644
--- a/include/verilated_types.h
+++ b/include/verilated_types.h
@@ -1477,7 +1477,7 @@ class VlClass VL_NOT_FINAL : public VlDeletable {
 
 public:
     // CONSTRUCTORS
-    VlClass() = default;
+    VlClass() { refCountInc(); }
     VlClass(const VlClass& copied) {}
     ~VlClass() override = default;
 };
@@ -1526,8 +1526,9 @@ public:
         // () required here to avoid narrowing conversion warnings,
         // when a new() has an e.g. CData type and passed a 1U.
         : m_objp{new T_Class(std::forward<T_Args>(args)...)} {
+        // refCountInc was moved to the constructor of T_Class
+        // to fix self references in constructor.
         m_objp->m_deleterp = &deleter;
-        refCountInc();
     }
     // Explicit to avoid implicit conversion from 0
     explicit VlClassRef(T_Class* objp)
diff --git a/test_regress/t/t_class_this_constructor.pl b/test_regress/t/t_class_this_constructor.pl
new file mode 100755
index 000000000..aabcde63e
--- /dev/null
+++ b/test_regress/t/t_class_this_constructor.pl
@@ -0,0 +1,21 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2020 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(simulator => 1);
+
+compile(
+    );
+
+execute(
+    check_finished => 1,
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_class_this_constructor.v b/test_regress/t/t_class_this_constructor.v
new file mode 100644
index 000000000..944d737db
--- /dev/null
+++ b/test_regress/t/t_class_this_constructor.v
@@ -0,0 +1,26 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2023 by Antmicro Ltd.
+// SPDX-License-Identifier: CC0-1.0
+
+class Cls;
+   bit x = 1'b0;
+   function new;
+      Cls c;
+      if (c == this) begin
+         x = 1'b1;
+      end
+   endfunction
+endclass
+
+module t (/*AUTOARG*/);
+   Cls c;
+   initial begin
+      c = new;
+      if (c.x) $stop;
+
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+endmodule