From a378dbd9b2e5380076bcfcdbf6cad2430b05fdd3 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Sat, 2 Mar 2024 10:14:54 -0500
Subject: [PATCH] Tests: Fix t_dist_whitespace

---
 test_regress/t/t_dist_whitespace.pl |  2 ++
 test_regress/t/t_lint_top_bad.v     | 12 ++++++------
 2 files changed, 8 insertions(+), 6 deletions(-)

diff --git a/test_regress/t/t_dist_whitespace.pl b/test_regress/t/t_dist_whitespace.pl
index 73ecea371..f1c28607e 100755
--- a/test_regress/t/t_dist_whitespace.pl
+++ b/test_regress/t/t_dist_whitespace.pl
@@ -10,6 +10,8 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 
 scenarios(dist => 1);
 
+my $root = "..";
+
 if (!-r "$root/.git") {
     skip("Not in a git repository");
 } else {
diff --git a/test_regress/t/t_lint_top_bad.v b/test_regress/t/t_lint_top_bad.v
index 9b35bc7e1..eb3ae9d37 100644
--- a/test_regress/t/t_lint_top_bad.v
+++ b/test_regress/t/t_lint_top_bad.v
@@ -5,10 +5,10 @@
 // SPDX-License-Identifier: CC0-1.0
 
 module sub(input wire clk, cpu_reset);
-   reg reset_r;	
-   always @(posedge clk) begin	
+   reg reset_r;
+   always @(posedge clk) begin
       reset_r <= cpu_reset;	 // The problematic one
-   end 
+   end
 endmodule
 
 module TOP(/*AUTOARG*/
@@ -19,14 +19,14 @@ module TOP(/*AUTOARG*/
    input clk;
    input reset_l;
 
-   reg   sync_0, sync_1, sync_2;	
-   wire  _cpu_reset_chain_io_q = sync_0;	
+   reg   sync_0, sync_1, sync_2;
+   wire  _cpu_reset_chain_io_q = sync_0;
 
    sub sub (.clk(clk),
             .cpu_reset(_cpu_reset_chain_io_q | !reset_l));
 
    always @(posedge clk) begin
-      sync_0 <= sync_1;	
+      sync_0 <= sync_1;
       sync_1 <= sync_2;
       sync_2 <= !reset_l;
    end