Add unique and parallel case

Changes

@@ -3,6 +3,10 @@ Revision history for Verilator
 The contributors that suggested a given feature are shown in [].  [by ...]
 indicates the contributor was also the author of the fix; Thanks!
 
+* Verilator 3.68**
+
+***  Add SystemVerilog unique and priority case.
+
 * Verilator 3.680 2008/10/08
 
 **   Support negative bit indexes. [Stephane Laurent]

bin/verilator

@@ -1038,7 +1038,8 @@ including function call-like preprocessor defines.
 
 Verilator supports ==? and !=? operators, $bits, $countones, $error,
 $fatal, $info, $isunknown, $onehot, $onehot0, $warning, always_comb,
-always_ff, always_latch, do-while, and final.
+always_ff, always_latch, do-while, final, priority case/if, and unique
+case/if.
 
 It also supports .name and .* interconnection.
 
@@ -1084,6 +1085,10 @@ formally prove the directive to be true, or failing that, will insert the
 appropriate code to detect failing cases at runtime and print an "Assertion
 failed" error message.
 
+Verilator likewise also asserts any "unique" or "priority" SystemVerilog
+keywords on case statements.  However, "unique if" and "priority if" are
+currently simply ignored.
+
 =head1 LANGUAGE EXTENSIONS
 
 The following additional constructs are the extensions Verilator supports
@@ -1545,6 +1550,11 @@ while, wire, xnor, xor
 
 Generally supported.
 
+=item priority if, unique if
+
+Priority and unique if's are treated as normal ifs and not asserted to be
+full nor unique.
+
 =item specify specparam
 
 All specify blocks and timing checks are ignored.

src/V3Read.h

@@ -31,6 +31,11 @@ class V3Lexer;
 class V3Number;
 class AstNode;
 
+//======================================================================
+// Types (between parser & lexer)
+
+typedef enum { uniq_NONE, uniq_UNIQUE, uniq_PRIORITY } V3UniqState;
+
 //============================================================================
 
 class V3Read {

src/verilog.l

@@ -355,7 +355,9 @@ escid	\\[^ \t\f\r\n]+
   "endproperty"		{yylval.fileline = CRELINE(); return yENDPROPERTY;}
   "final"		{yylval.fileline = CRELINE(); return yFINAL;}
   "iff"			{yylval.fileline = CRELINE(); return yIFF;}
+  "priority"		{yylval.fileline = CRELINE(); return yPRIORITY;}
   "static"		{yylval.fileline = CRELINE(); return ySTATIC;}
+  "unique"		{yylval.fileline = CRELINE(); return yUNIQUE;}
   /*     Generic unsupported warnings */
   /* Note assert_strobe was in SystemVerilog 3.1, but removed for SystemVerilog 2005 */
   "alias"		{yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);}
@@ -406,7 +408,6 @@ escid	\\[^ \t\f\r\n]+
   "null"		{yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);}
   "package"		{yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);}
   "packed"		{yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);}
-  "priority"		{yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);}
   "program"		{yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);}
   "protected"		{yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);}
   "pure"		{yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);}
@@ -429,7 +430,6 @@ escid	\\[^ \t\f\r\n]+
   "timeunit"		{yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);}
   "type"		{yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);}
   "typedef"		{yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);}
-  "unique"		{yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);}
   "var"			{yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);}
   "virtual"		{yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);}
   "void"		{yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);}

src/verilog.y

@@ -57,6 +57,7 @@ public:
     static string	s_instModule;	// Name of module referenced for instantiations
     static AstPin*	s_instParamp;	// Parameters for instantiations
     static bool		s_trace;	// Tracing is turned on
+    static int		s_uniqueAttr;	// Bitmask of unique/priority keywords
 
     static AstVar*  createVariable(FileLine* fileline, string name, AstRange* arrayp);
     static AstNode* createSupplyExpr(FileLine* fileline, string name, int value);
@@ -107,6 +108,7 @@ class AstSenTree;
     string*	strp;
     int 	cint;
     double	cdouble;
+    V3UniqState	uniqstate;
 
     AstNode*	nodep;
 
@@ -201,6 +203,7 @@ class AstSenTree;
 %token<fileline>	yOUTPUT		"output"
 %token<fileline>	yPARAMETER	"parameter"
 %token<fileline>	yPOSEDGE	"posedge"
+%token<fileline>	yPRIORITY	"priority"
 %token<fileline>	yPROPERTY	"property"
 %token<fileline>	yREG		"reg"
 %token<fileline>	ySCALARED	"scalared"
@@ -212,6 +215,7 @@ class AstSenTree;
 %token<fileline>	yTASK		"task"
 %token<fileline>	yTRI		"tri"
 %token<fileline>	yTRUE		"true"
+%token<fileline>	yUNIQUE		"unique"
 %token<fileline>	yUNSIGNED	"unsigned"
 %token<fileline>	yVECTORED	"vectored"
 %token<fileline>	yWHILE		"while"
@@ -982,10 +986,20 @@ stmt<nodep>:
 //************************************************
 // Case/If
 
+unique_priorityE<uniqstate>:
+		/*empty*/				{ $$ = uniq_NONE; }
+	|	yPRIORITY				{ $$ = uniq_PRIORITY; }
+	|	yUNIQUE					{ $$ = uniq_UNIQUE; }
+	;
+
 stateCaseForIf<nodep>:
-		caseStmt caseAttrE caseListE yENDCASE	{ $$ = $1; if ($3) $1->addItemsp($3); }
-	|	yIF '(' expr ')' stmtBlock	%prec prLOWER_THAN_ELSE	{ $$ = new AstIf($1,$3,$5,NULL); }
-	|	yIF '(' expr ')' stmtBlock yELSE stmtBlock		{ $$ = new AstIf($1,$3,$5,$7); }
+		unique_priorityE caseStmt caseAttrE caseListE yENDCASE	{ $$ = $2; if ($4) $2->addItemsp($4);
+							  if ($1 == uniq_UNIQUE) $2->parallelPragma(true);
+							  if ($1 == uniq_PRIORITY) $2->fullPragma(true); }
+	|	unique_priorityE yIF '(' expr ')' stmtBlock	%prec prLOWER_THAN_ELSE
+							{ $$ = new AstIf($2,$4,$6,NULL); }
+	|	unique_priorityE yIF '(' expr ')' stmtBlock yELSE stmtBlock
+							{ $$ = new AstIf($2,$4,$6,$8); }
 	|	yFOR '(' varRefBase '=' expr ';' expr ';' varRefBase '=' expr ')' stmtBlock
 							{ $$ = new AstFor($1, new AstAssign($4,$3,$5)
 									  ,$7, new AstAssign($10,$9,$11)

test_regress/t/t_assert_synth.v

@@ -32,6 +32,12 @@ module t (/*AUTOARG*/
 	2'b1_0: ;
 	// Note no default
       endcase
+      priority case ({a,b_fc})
+	2'b0_0: ;
+	2'b0_1: ;
+	2'b1_0: ;
+	// Note no default
+      endcase
    end
 
    always @* begin