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Tests: Fix t_math_svl.pl
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@ -47,6 +47,23 @@ module t (/*AUTOARG*/
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cyc_d1 <= cyc_com;
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end
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initial begin
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// Constification check
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if ($countones(32'b11001011101) != 7) $stop;
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if ($countones(32'b0) != 0) $stop;
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if ($isunknown(32'b11101x11111) != 1) $stop;
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if ($isunknown(32'b11101011111) != 0) $stop;
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if ($isunknown(32'b10zzzzzzzzz) != 1) $stop;
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if ($bits(0) != 32'd32) $stop;
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if ($bits(lc) != 5) $stop;
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if ($onehot(32'b00000001000000) != 1'b1) $stop;
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if ($onehot(32'b00001001000000) != 1'b0) $stop;
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if ($onehot(32'b0) != 1'b0) $stop;
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if ($onehot0(32'b00000001000000) != 1'b1) $stop;
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if ($onehot0(32'b00001001000000) != 1'b0) $stop;
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if ($onehot0(32'b0) != 1'b1) $stop;
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end
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always @ (posedge clk) begin
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if (cyc!=0) begin
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cyc <= cyc + 1;
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@ -54,22 +71,6 @@ module t (/*AUTOARG*/
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// cyc, l, lc, lo, l0, q,qc,qo,q0, w,wc,wo,w0);
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if (cyc_com != cyc_com) $stop;
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if (cyc_d1 != cyc-1) $stop;
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if (cyc==0) begin
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// Constification check
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if ($countones(32'b11001011101) != 7) $stop;
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if ($countones(32'b0) != 0) $stop;
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if ($isunknown(32'b11101x11111) != 1) $stop;
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if ($isunknown(32'b11101011111) != 0) $stop;
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if ($isunknown(32'b10zzzzzzzzz) != 0) $stop;
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if ($bits(0) != 32'd32) $stop;
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if ($bits(lc) != 5) $stop;
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if ($onehot(32'b00000001000000) != 1'b1) $stop;
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if ($onehot(32'b00001001000000) != 1'b0) $stop;
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if ($onehot(32'b0) != 1'b0) $stop;
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if ($onehot0(32'b00000001000000) != 1'b1) $stop;
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if ($onehot0(32'b00001001000000) != 1'b0) $stop;
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if ($onehot0(32'b0) != 1'b1) $stop;
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end
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if (cyc==1) begin
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l <= 16'b0;
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q <= 50'h0;
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