From a24f61403a56907ebfa266583e94b0d0d0629dc4 Mon Sep 17 00:00:00 2001
From: Kevin Nygaard <nygaard@ibm.com>
Date: Sat, 16 Mar 2024 18:02:37 -0500
Subject: [PATCH] Support implicitly-typed variable definitions in for-loop
 initializers (#4945) (#4986)

- Adds support for C-style for-loop initializers
    - Current implementation supports: for (x a = 1, y b = 2, ...)
    - This patch extends support to:   for (x a = 1,   b = 2, ...)
- Adds unit test for new feature
---
 src/verilog.y                | 18 +++++++++++++++---
 test_regress/t/t_for_comma.v |  2 ++
 2 files changed, 17 insertions(+), 3 deletions(-)

diff --git a/src/verilog.y b/src/verilog.y
index 813f9e449..edc3410cd 100644
--- a/src/verilog.y
+++ b/src/verilog.y
@@ -3701,13 +3701,16 @@ statement_item<nodep>:          // IEEE: statement_item
         ;
 
 statementFor<beginp>:           // IEEE: part of statement
-                yFOR '(' for_initialization expr ';' for_stepE ')' stmtBlock
+                yFOR beginForParen for_initialization expr ';' for_stepE ')' stmtBlock
                         { $$ = new AstBegin{$1, "", $3, false, true};
                           $$->addStmtsp(new AstWhile{$1, $4, $8, $6}); }
-        |       yFOR '(' for_initialization ';' for_stepE ')' stmtBlock
+        |       yFOR beginForParen for_initialization ';' for_stepE ')' stmtBlock
                         { $$ = new AstBegin{$1, "", $3, false, true};
                           $$->addStmtsp(new AstWhile{$1, new AstConst{$1, AstConst::BitTrue{}}, $7, $5}); }
         ;
+beginForParen:  // IEEE: Part of statement (for loop beginning paren)
+                '('                                     { VARRESET(); }
+        ;
 
 statementVerilatorPragmas<nodep>:
                 yVL_COVERAGE_BLOCK_OFF
@@ -3997,7 +4000,16 @@ for_initializationItem<nodep>:          // IEEE: variable_assignment + for_varia
                           $$->addNext(new AstAssign{$4, new AstParseRef{$<fl>3, VParseRefExp::PX_TEXT, *$3}, $5}); }
         //                      // IEEE: variable_assignment
         //                      // UNSUP variable_lvalue below
-        |       varRefBase '=' expr                     { $$ = new AstAssign{$2, $1, $3}; }
+        |       id/*newOrExisting*/ '=' expr
+                        { if (GRAMMARP->m_varDecl) {
+                              AstVar* const varp = VARDONEA($<fl>1, *$1, nullptr, nullptr);
+                              varp->lifetime(VLifetime::AUTOMATIC);
+                              $$ = varp;
+                              $$->addNext(new AstAssign{$2, new AstParseRef{$<fl>1, VParseRefExp::PX_TEXT, *$1}, $3});
+                          } else {
+                              $$ = new AstAssign{$2, new AstParseRef{$<fl>1, VParseRefExp::PX_TEXT, *$1}, $3};
+                          }
+                        }
         ;
 
 for_stepE<nodep>:               // IEEE: for_step + empty
diff --git a/test_regress/t/t_for_comma.v b/test_regress/t/t_for_comma.v
index 86ae62a87..81f8f2ddf 100644
--- a/test_regress/t/t_for_comma.v
+++ b/test_regress/t/t_for_comma.v
@@ -54,6 +54,8 @@ module t (/*AUTOARG*/);
       `checkc(7);
       for (int a = 1, int b = 1; a < 3; a = a + 1, b = b + 1) begin c = c + 1 + a + b; end
       `checkc(8);
+      for (int a = 1, x = 1; a < 3; a = a + 1, x = x + 1) begin c = c + 1 + a + x; end
+      `checkc(8);
       $write("*-* All Finished *-*\n");
       $finish;
    end