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Update Bison parser to track Verilog-Perl 3.110. No functional change
This commit is contained in:
Wilson Snyder
parent
290795a76b
commit
a199f4a849
246
src/verilog.y
246
src/verilog.y
@ -129,9 +129,13 @@ class AstSenTree;
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AstVarRef* varrefp;
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}
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// When writing Bison patterns we use yTOKEN instead of "token",
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// so Bison will error out on unknown "token"s.
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// Generic lexer tokens, for example a number
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// IEEE: real_number
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%token<cdouble> yaFLOATNUM "FLOATING-POINT NUMBER"
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// IEEE: identifier, class_identifier, class_variable_identifier,
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// covergroup_variable_identifier, dynamic_array_variable_identifier,
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// enum_identifier, interface_identifier, interface_instance_identifier,
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@ -153,6 +157,33 @@ class AstSenTree;
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%token<strp> yaSCCTOR "`systemc_implementation BLOCK"
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%token<strp> yaSCDTOR "`systemc_imp_header BLOCK"
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%token<fileline> '!'
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%token<fileline> '#'
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%token<fileline> '%'
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%token<fileline> '&'
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%token<fileline> '('
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%token<fileline> ')'
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%token<fileline> '*'
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%token<fileline> '+'
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%token<fileline> ','
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%token<fileline> '-'
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%token<fileline> '.'
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%token<fileline> '/'
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%token<fileline> ':'
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%token<fileline> ';'
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%token<fileline> '<'
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%token<fileline> '='
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%token<fileline> '>'
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%token<fileline> '?'
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%token<fileline> '@'
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%token<fileline> '['
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%token<fileline> ']'
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%token<fileline> '^'
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%token<fileline> '{'
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%token<fileline> '|'
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%token<fileline> '}'
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%token<fileline> '~'
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// Specific keywords
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// yKEYWORD means match "keyword"
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// Other cases are yXX_KEYWORD where XX makes it unique,
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@ -335,33 +366,6 @@ class AstSenTree;
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%token<fileline> yPSL_KET "}"
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%token<fileline> yP_LOGIFF
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%token<fileline> '!'
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%token<fileline> '#'
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%token<fileline> '%'
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%token<fileline> '&'
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%token<fileline> '('
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%token<fileline> ')'
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%token<fileline> '*'
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%token<fileline> '+'
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%token<fileline> ','
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%token<fileline> '-'
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%token<fileline> '.'
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%token<fileline> '/'
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%token<fileline> ':'
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%token<fileline> ';'
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%token<fileline> '<'
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%token<fileline> '='
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%token<fileline> '>'
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%token<fileline> '?'
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%token<fileline> '@'
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%token<fileline> '['
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%token<fileline> ']'
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%token<fileline> '^'
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%token<fileline> '{'
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%token<fileline> '|'
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%token<fileline> '}'
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%token<fileline> '~'
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// [* is not a operator, as "[ * ]" is legal
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// [= and [-> could be repitition operators, but to match [* we don't add them.
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// '( is not a operator, as "' (" is legal
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@ -396,10 +400,6 @@ class AstSenTree;
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%nonassoc prLOWER_THAN_ELSE
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%nonassoc yELSE
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// Types are in same order as declarations.
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// Naming:
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// Trailing E indicates this type may have empty match
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//BISONPRE_TYPES
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// Blank lines for type insertion
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// Blank lines for type insertion
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@ -448,11 +448,12 @@ descriptionList: // IEEE: part of source_text
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description: // ==IEEE: description
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module_declaration { }
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// | interfaceDecl { }
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// | interface_declaration { }
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// | program_declaration { }
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// | package_declaration { }
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// | package_declaration { }
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// | package_item { }
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// | bind_directive { }
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// unsupported // IEEE: config_declaration
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| error { }
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;
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@ -473,7 +474,7 @@ module_declaration: // ==IEEE: module_declaration (incomplete)
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;
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modHeader<modulep>: // IEEE: module_nonansi_header + module_ansi_header
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modHdr parameter_port_listE modPortsE ';'
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modHdr parameter_port_listE modPortsStarE ';'
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{ $1->modTrace(v3Global.opt.trace() && $1->fileline()->tracingOn()); // Stash for implicit wires, etc
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if ($2) $1->addStmtp($2); if ($3) $1->addStmtp($3); }
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;
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@ -507,7 +508,7 @@ modParSecond<nodep>:
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| param { $$ = $1; }
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;
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modPortsE<nodep>:
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modPortsStarE<nodep>:
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/* empty */ { $$ = NULL; }
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| '(' ')' { $$ = NULL; }
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| '(' {V3Parse::s_pinNum=1;} portList ')' { $$ = $3; }
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@ -637,10 +638,8 @@ module_itemList<nodep>: // IEEE: Part of module_declaration
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module_item<nodep>: // ==IEEE: module_item
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// // IEEE: non_port_module_item
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generate_region { $$ = $1; }
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| modOrGenItem { $$ = $1; }
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// // IEEE: specify_block
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| ySPECIFY specifyJunkList yENDSPECIFY { $$ = NULL; }
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| ySPECIFY yENDSPECIFY { $$ = NULL; }
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| module_or_generate_item { $$ = $1; }
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| specify_block { $$ = $1; }
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// // Verilator specific
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| yaSCHDR { $$ = new AstScHdr(CRELINE(),*$1); }
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| yaSCINT { $$ = new AstScInt(CRELINE(),*$1); }
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@ -658,18 +657,15 @@ generate_region<nodep>: // ==IEEE: generate_region
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;
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// IEEE: module_or_generate_item + module_common_item + parameter_override
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modOrGenItem<nodep>:
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module_or_generate_item<nodep>:
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// // IEEE: always_construct
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yALWAYS event_controlE stmtBlock { $$ = new AstAlways($1,$2,$3); }
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// // IEEE: initial_construct
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| yINITIAL stmtBlock { $$ = new AstInitial($1,$2); }
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// // IEEE: final_construct
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| yFINAL stmtBlock { $$ = new AstFinal($1,$2); }
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// // IEEE: continuous_assign
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| yASSIGN delayE assignList ';' { $$ = $3; }
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| continuous_assign { $$ = $1; }
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| initial_construct { $$ = $1; }
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| final_construct { $$ = $1; }
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| yDEFPARAM list_of_defparam_assignments ';' { $$ = $2; }
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| instDecl { $$ = $1; }
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| taskDecl { $$ = $1; }
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| task_declaration { $$ = $1; }
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| function_declaration { $$ = $1; }
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| gateDecl { $$ = $1; }
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| portDecl { $$ = $1; }
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@ -678,15 +674,25 @@ modOrGenItem<nodep>:
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| pslStmt { $$ = $1; }
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| concurrent_assertion_item { $$ = $1; } // IEEE puts in module_item; seems silly
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| clocking_declaration { $$ = $1; }
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;
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| error ';' { $$ = NULL; }
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continuous_assign<nodep>: // IEEE: continuous_assign
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yASSIGN delayE assignList ';' { $$ = $3; }
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;
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initial_construct<nodep>: // IEEE: initial_construct
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yINITIAL stmtBlock { $$ = new AstInitial($1,$2); }
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;
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final_construct<nodep>: // IEEE: final_construct
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yFINAL stmtBlock { $$ = new AstFinal($1,$2); }
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;
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//************************************************
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// Generates
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// Because genItemList includes variable declarations, we don't need beginNamed
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genItemBlock<nodep>:
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generate_block_or_null<nodep>: // IEEE: generate_block_or_null
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genItem { $$ = new AstBegin(CRELINE(),"genblk",$1); }
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| genItemBegin { $$ = $1; }
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;
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@ -699,6 +705,8 @@ genTopBlock<nodep>:
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genItemBegin<nodep>: // IEEE: part of generate_block
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yBEGIN genItemList yEND { $$ = new AstBegin($1,"genblk",$2); }
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| yBEGIN yEND { $$ = NULL; }
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| yaID ':' yBEGIN genItemList yEND endLabelE { $$ = new AstBegin($2,*$1,$4); }
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| yaID ':' yBEGIN yEND endLabelE { $$ = NULL; }
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| yBEGIN ':' yaID genItemList yEND endLabelE { $$ = new AstBegin($2,*$3,$4); }
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| yBEGIN ':' yaID yEND endLabelE { $$ = NULL; }
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;
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@ -708,31 +716,39 @@ genItemList<nodep>:
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| genItemList genItem { $$ = $1->addNextNull($2); }
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;
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genItem<nodep>:
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// // IEEE: module_or_interface_or_generate_item (INCOMPLETE)
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modOrGenItem { $$ = $1; }
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| yCASE '(' expr ')' genCaseListE yENDCASE { $$ = new AstGenCase($1,$3,$5); }
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| yIF '(' expr ')' genItemBlock %prec prLOWER_THAN_ELSE { $$ = new AstGenIf($1,$3,$5,NULL); }
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| yIF '(' expr ')' genItemBlock yELSE genItemBlock { $$ = new AstGenIf($1,$3,$5,$7); }
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// // IEEE: loop_generate_construct
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| yFOR '(' varRefBase '=' expr ';' expr ';' varRefBase '=' expr ')' genItemBlock
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{ $$ = new AstGenFor($1, new AstAssign($4,$3,$5)
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,$7, new AstAssign($10,$9,$11)
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,$13);}
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genItem<nodep>: // IEEE: module_or_interface_or_generate_item (INCOMPLETE)
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module_or_generate_item { $$ = $1; }
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| conditional_generate_construct {}
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| loop_generate_construct {}
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;
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genCaseListE<nodep>:
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conditional_generate_construct<nodep>: // ==IEEE: conditional_generate_construct
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yCASE '(' expr ')' case_generate_itemListE yENDCASE { $$ = new AstGenCase($1,$3,$5); }
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| yIF '(' expr ')' generate_block_or_null %prec prLOWER_THAN_ELSE { $$ = new AstGenIf($1,$3,$5,NULL); }
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| yIF '(' expr ')' generate_block_or_null yELSE generate_block_or_null { $$ = new AstGenIf($1,$3,$5,$7); }
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;
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loop_generate_construct<nodep>: // ==IEEE: loop_generate_construct
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yFOR '(' varRefBase '=' expr ';' expr ';' varRefBase '=' expr ')' generate_block_or_null
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{ $$ = new AstGenFor($1, new AstAssign($4,$3,$5)
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,$7, new AstAssign($10,$9,$11)
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,$13);}
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;
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case_generate_itemListE<nodep>: // IEEE: [{ case_generate_itemList }]
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/* empty */ { $$ = NULL; }
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| genCaseList { $$ = $1; }
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| case_generate_itemList { $$ = $1; }
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;
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genCaseList<nodep>:
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caseCondList ':' genItemBlock { $$ = new AstCaseItem($2,$1,$3); }
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| yDEFAULT ':' genItemBlock { $$ = new AstCaseItem($2,NULL,$3); }
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| yDEFAULT genItemBlock { $$ = new AstCaseItem($1,NULL,$2); }
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| genCaseList caseCondList ':' genItemBlock { $$ = $1;$1->addNext(new AstCaseItem($3,$2,$4)); }
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| genCaseList yDEFAULT genItemBlock { $$ = $1;$1->addNext(new AstCaseItem($2,NULL,$3)); }
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| genCaseList yDEFAULT ':' genItemBlock { $$ = $1;$1->addNext(new AstCaseItem($3,NULL,$4)); }
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case_generate_itemList<nodep>: // IEEE: { case_generate_itemList }
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case_generate_item { $$=$1; }
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| case_generate_itemList case_generate_item { $$=$1; $1->addNext($2); }
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;
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case_generate_item<nodep>: // ==IEEE: case_generate_item
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caseCondList ':' generate_block_or_null { $$ = new AstCaseItem($2,$1,$3); }
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| yDEFAULT ':' generate_block_or_null { $$ = new AstCaseItem($2,NULL,$3); }
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| yDEFAULT generate_block_or_null { $$ = new AstCaseItem($1,NULL,$2); }
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;
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//************************************************
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@ -931,7 +947,7 @@ event_controlE<sentreep>:
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event_control<sentreep>: // ==IEEE: event_control
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'@' '(' senList ')' { $$ = new AstSenTree($1,$3); }
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| '@' senitemVar { $$ = new AstSenTree($1,$2); } /* For events only */
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| '@' '(' '*' ')' { $$ = NULL; } /* Verilog 2001 */
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| '@' '(' '*' ')' { $$ = NULL; }
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| '@' '*' { $$ = NULL; } /* Verilog 2001 */
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;
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@ -982,20 +998,39 @@ stmtList<nodep>:
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// IEEE: statement_or_null (may include more stuff, not analyzed)
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// == function_statement_or_null
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stmt<nodep>:
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// // from _or_null
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';' { $$ = NULL; }
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| labeledStmt { $$ = $1; }
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| yaID ':' labeledStmt { $$ = new AstBegin($2, *$1, $3); } /*S05 block creation rule*/
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// // IEEE: nonblocking_assignment
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| varRefDotBit yP_LTE delayE expr ';' { $$ = new AstAssignDly($2,$1,$4); }
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| delay_control stmtBlock { $$ = $2; $1->v3warn(STMTDLY,"Ignoring delay on this delayed statement.\n"); }
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// // IEEE: operator_assignment
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| varRefDotBit '=' delayE expr ';' { $$ = new AstAssign($2,$1,$4); }
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| varRefDotBit '=' yD_FOPEN '(' expr ',' expr ')' ';' { $$ = new AstFOpen($3,$1,$5,$7); }
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| yASSIGN varRefDotBit '=' delayE expr ';' { $$ = new AstAssign($1,$2,$5); }
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| '{' identifier_listLvalue '}' yP_LTE delayE expr ';' { $$ = new AstAssignDly($4,$2,$6); }
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| '{' identifier_listLvalue '}' '=' delayE expr ';' { $$ = new AstAssign($4,$2,$6); }
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// // IEEE: nonblocking_assignment
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| varRefDotBit yP_LTE delayE expr ';' { $$ = new AstAssignDly($2,$1,$4); }
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| '{' identifier_listLvalue '}' yP_LTE delayE expr ';' { $$ = new AstAssignDly($4,$2,$6); }
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// // IEEE: procedural_continuous_assignment
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| yASSIGN varRefDotBit '=' delayE expr ';' { $$ = new AstAssign($1,$2,$5); }
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// // IEEE: case_statement
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| unique_priorityE caseStart caseAttrE case_itemListE yENDCASE { $$ = $2; if ($4) $2->addItemsp($4);
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if ($1 == uniq_UNIQUE) $2->parallelPragma(true);
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if ($1 == uniq_PRIORITY) $2->fullPragma(true); }
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// // IEEE: conditional_statement
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| unique_priorityE yIF '(' expr ')' stmtBlock %prec prLOWER_THAN_ELSE
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{ $$ = new AstIf($2,$4,$6,NULL); }
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| unique_priorityE yIF '(' expr ')' stmtBlock yELSE stmtBlock
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{ $$ = new AstIf($2,$4,$6,$8); }
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// // IEEE: subroutine_call_statement (INCOMPLETE)
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| taskRef ';' { $$ = $1; }
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| yD_C '(' cStrList ')' ';' { $$ = (v3Global.opt.ignc() ? NULL : new AstUCStmt($1,$3)); }
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| yD_FCLOSE '(' varRefDotBit ')' ';' { $$ = new AstFClose($1, $3); }
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| yD_FFLUSH ';' { $1->v3error("Unsupported: $fflush of all handles does not map to C++.\n"); }
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@ -1006,8 +1041,6 @@ stmt<nodep>:
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| yD_STOP parenE ';' { $$ = new AstStop($1); }
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| yD_STOP '(' expr ')' ';' { $$ = new AstStop($1); }
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| yVL_COVERAGE_BLOCK_OFF { $$ = new AstPragma($1,AstPragmaType::COVERAGE_BLOCK_OFF); }
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| stateCaseForIf { $$ = $1; }
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| taskRef ';' { $$ = $1; }
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| yD_DISPLAY parenE ';' { $$ = new AstDisplay($1,AstDisplayType::DISPLAY,"", NULL,NULL); }
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| yD_DISPLAY '(' yaSTRING commaEListE ')' ';' { $$ = new AstDisplay($1,AstDisplayType::DISPLAY,*$3,NULL,$4); }
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@ -1030,6 +1063,14 @@ stmt<nodep>:
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| yD_READMEMH '(' expr ',' varRefMem ')' ';' { $$ = new AstReadMem($1,true, $3,$5,NULL,NULL); }
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| yD_READMEMH '(' expr ',' varRefMem ',' expr ')' ';' { $$ = new AstReadMem($1,true, $3,$5,$7,NULL); }
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| yD_READMEMH '(' expr ',' varRefMem ',' expr ',' expr ')' ';' { $$ = new AstReadMem($1,true, $3,$5,$7,$9); }
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// // IEEE: loop_statement (INCOMPLETE)
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| yWHILE '(' expr ')' stmtBlock { $$ = new AstWhile($1,$3,$5);}
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| yFOR '(' varRefBase '=' expr ';' expr ';' varRefBase '=' expr ')' stmtBlock
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{ $$ = new AstFor($1, new AstAssign($4,$3,$5)
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,$7, new AstAssign($10,$9,$11)
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,$13);}
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| yDO stmtBlock yWHILE '(' expr ')' { $$ = $2->cloneTree(true); $$->addNext(new AstWhile($1,$5,$2));}
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;
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//************************************************
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@ -1041,23 +1082,7 @@ unique_priorityE<uniqstate>: // IEEE: unique_priority + empty
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| yUNIQUE { $$ = uniq_UNIQUE; }
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;
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stateCaseForIf<nodep>:
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unique_priorityE caseStmt caseAttrE case_itemListE yENDCASE { $$ = $2; if ($4) $2->addItemsp($4);
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if ($1 == uniq_UNIQUE) $2->parallelPragma(true);
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if ($1 == uniq_PRIORITY) $2->fullPragma(true); }
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| unique_priorityE yIF '(' expr ')' stmtBlock %prec prLOWER_THAN_ELSE
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{ $$ = new AstIf($2,$4,$6,NULL); }
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| unique_priorityE yIF '(' expr ')' stmtBlock yELSE stmtBlock
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{ $$ = new AstIf($2,$4,$6,$8); }
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| yFOR '(' varRefBase '=' expr ';' expr ';' varRefBase '=' expr ')' stmtBlock
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{ $$ = new AstFor($1, new AstAssign($4,$3,$5)
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,$7, new AstAssign($10,$9,$11)
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,$13);}
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| yWHILE '(' expr ')' stmtBlock { $$ = new AstWhile($1,$3,$5);}
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| yDO stmtBlock yWHILE '(' expr ')' { $$ = $2->cloneTree(true); $$->addNext(new AstWhile($1,$5,$2));}
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;
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caseStmt<casep>:
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caseStart<casep>: // IEEE: part of case_statement
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yCASE '(' expr ')' { $$ = V3Parse::s_caseAttrp = new AstCase($1,AstCaseType::CASE,$3,NULL); }
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| yCASEX '(' expr ')' { $$ = V3Parse::s_caseAttrp = new AstCase($1,AstCaseType::CASEX,$3,NULL); $1->v3warn(CASEX,"Suggest casez (with ?'s) in place of casex (with X's)\n"); }
|
||||
| yCASEZ '(' expr ')' { $$ = V3Parse::s_caseAttrp = new AstCase($1,AstCaseType::CASEZ,$3,NULL); }
|
||||
@ -1091,25 +1116,25 @@ caseCondList<nodep>: // IEEE: part of case_item
|
||||
//************************************************
|
||||
// Functions/tasks
|
||||
|
||||
taskRef<nodep>:
|
||||
taskRef<nodep>: // IEEE: part of tf_call
|
||||
idDotted { $$ = new AstTaskRef(CRELINE(),new AstParseRef($1->fileline(), AstParseRefExp::TASK, $1),NULL);}
|
||||
| idDotted '(' exprList ')' { $$ = new AstTaskRef(CRELINE(),new AstParseRef($1->fileline(), AstParseRefExp::TASK, $1),$3);}
|
||||
;
|
||||
|
||||
funcRef<nodep>:
|
||||
funcRef<nodep>: // IEEE: part of tf_call
|
||||
idDotted '(' exprList ')' { $$ = new AstFuncRef($2,new AstParseRef($1->fileline(), AstParseRefExp::FUNC, $1), $3); }
|
||||
;
|
||||
|
||||
taskDecl<nodep>:
|
||||
yTASK lifetimeE yaID funcGuts yENDTASK endLabelE
|
||||
task_declaration<nodep>: // ==IEEE: task_declaration
|
||||
yTASK lifetimeE yaID tfGuts yENDTASK endLabelE
|
||||
{ $$ = new AstTask ($1,*$3,$4);}
|
||||
;
|
||||
|
||||
function_declaration<funcp>: // IEEE: function_declaration + function_body_declaration
|
||||
yFUNCTION lifetimeE funcTypeE yaID funcGuts yENDFUNCTION endLabelE { $$ = new AstFunc ($1,*$4,$5,$3); }
|
||||
| yFUNCTION lifetimeE ySIGNED funcTypeE yaID funcGuts yENDFUNCTION endLabelE { $$ = new AstFunc ($1,*$5,$6,$4); $$->isSigned(true); }
|
||||
| yFUNCTION lifetimeE funcTypeE yaID yVL_ISOLATE_ASSIGNMENTS funcGuts yENDFUNCTION endLabelE { $$ = new AstFunc ($1,*$4,$6,$3); $$->attrIsolateAssign(true);}
|
||||
| yFUNCTION lifetimeE ySIGNED funcTypeE yaID yVL_ISOLATE_ASSIGNMENTS funcGuts yENDFUNCTION endLabelE { $$ = new AstFunc ($1,*$5,$7,$4); $$->attrIsolateAssign(true); $$->isSigned(true); }
|
||||
yFUNCTION lifetimeE funcTypeE yaID tfGuts yENDFUNCTION endLabelE { $$ = new AstFunc ($1,*$4,$5,$3); }
|
||||
| yFUNCTION lifetimeE ySIGNED funcTypeE yaID tfGuts yENDFUNCTION endLabelE { $$ = new AstFunc ($1,*$5,$6,$4); $$->isSigned(true); }
|
||||
| yFUNCTION lifetimeE funcTypeE yaID yVL_ISOLATE_ASSIGNMENTS tfGuts yENDFUNCTION endLabelE { $$ = new AstFunc ($1,*$4,$6,$3); $$->attrIsolateAssign(true);}
|
||||
| yFUNCTION lifetimeE ySIGNED funcTypeE yaID yVL_ISOLATE_ASSIGNMENTS tfGuts yENDFUNCTION endLabelE { $$ = new AstFunc ($1,*$5,$7,$4); $$->attrIsolateAssign(true); $$->isSigned(true); }
|
||||
;
|
||||
|
||||
lifetimeE: // IEEE: lifetime - plus empty
|
||||
@ -1118,12 +1143,12 @@ lifetimeE: // IEEE: lifetime - plus empty
|
||||
| yAUTOMATIC { }
|
||||
;
|
||||
|
||||
funcGuts<nodep>:
|
||||
'(' {V3Parse::s_pinNum=1;} portV2kArgs ')' ';' funcBody { $$ = $3->addNextNull($6); }
|
||||
| ';' funcBody { $$ = $2; }
|
||||
tfGuts<nodep>:
|
||||
'(' {V3Parse::s_pinNum=1;} portV2kArgs ')' ';' tfBody { $$ = $3->addNextNull($6); }
|
||||
| ';' tfBody { $$ = $2; }
|
||||
;
|
||||
|
||||
funcBody<nodep>:
|
||||
tfBody<nodep>: // IEEE: part of function_body_declaration/task_body_declaration
|
||||
funcVarList stmtBlock { $$ = $1;$1->addNextNull($2); }
|
||||
| stmtBlock { $$ = $1; }
|
||||
;
|
||||
@ -1203,6 +1228,8 @@ exprNoStr<nodep>:
|
||||
| expr '?' expr ':' expr { $$ = new AstCond($2,$1,$3,$5); }
|
||||
| '(' expr ')' { $$ = $2; }
|
||||
| '_' '(' statePushVlg expr statePop ')' { $$ = $4; } // Arbitrary Verilog inside PSL
|
||||
|
||||
// // IEEE: concatenation/constant_concatenation
|
||||
| '{' cateList '}' { $$ = $2; }
|
||||
| '{' constExpr '{' cateList '}' '}' { $$ = new AstReplicate($1,$4,$2); }
|
||||
|
||||
@ -1231,6 +1258,8 @@ exprNoStr<nodep>:
|
||||
| yaINTNUM { $$ = new AstConst(CRELINE(),*$1); }
|
||||
|
||||
| varRefDotBit { $$ = $1; }
|
||||
|
||||
| error ';' { $$ = NULL; }
|
||||
;
|
||||
|
||||
// Generic expressions
|
||||
@ -1412,6 +1441,11 @@ gateXorPinList<nodep>:
|
||||
//************************************************
|
||||
// Specify
|
||||
|
||||
specify_block<nodep>: // ==IEEE: specify_block
|
||||
ySPECIFY specifyJunkList yENDSPECIFY { $$ = NULL; }
|
||||
| ySPECIFY yENDSPECIFY { $$ = NULL; }
|
||||
;
|
||||
|
||||
specifyJunkList:
|
||||
specifyJunk { } /* ignored */
|
||||
| specifyJunkList specifyJunk { } /* ignored */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user