diff --git a/Changes b/Changes index 63f6a978b..1cbddc1f2 100644 --- a/Changes +++ b/Changes @@ -75,7 +75,7 @@ Verilator 5.002 2022-10-29 * Fix linker errors in user-facing timing functions (#3657). [Krzysztof Bieganski, Antmicro Ltd] * Fix null access on optimized-out fork statements (#3658). [Krzysztof Bieganski, Antmicro Ltd] * Fix VPI inline module naming mismatch (#3690) (#3694). [Jiuyang Liu] -* Fix deadlock in timeprecision when using systemC (#3707). [Kamil Rakoczy, Antmicro Ltd] +* Fix deadlock in timeprecision when using SystemC (#3707). [Kamil Rakoczy, Antmicro Ltd] * Fix width mismatch on inside operator (#3714). [Alex Torregrosa] @@ -2987,7 +2987,7 @@ Verilator 3.502 2005-11-30 Stable * Fix local non-IO variables in public functions and tasks. * Fix bad lifetime optimization when same signal is assigned multiple - times in both branch of a if. [Danny Ding] + times in both branch of an if. [Danny Ding] Verilator 3.501 2005-11-16 Stable @@ -3127,8 +3127,8 @@ Verilator 3.450 2005-07-12 * $finish will no longer exit, but set Verilated::gotFinish(). This enables support for final statements, and for other cleanup code. If this is undesired, redefine the vl_user_finish routine. Top level - loops should use Verilated::gotFinish() as a exit condition for their - loop, and then call top->final(). To prevent a infinite loop, a double + loops should use Verilated::gotFinish() as an exit condition for their + loop, and then call top->final(). To prevent an infinite loop, a double $finish will still exit; this may be removed in future releases. * Support SystemVerilog keywords $bits, $countones, $isunknown, $onehot, $onehot0, always_comb, always_ff, always_latch, finish. @@ -3529,7 +3529,7 @@ Verilator 3.201-beta 2003-12-10 **Major:** * BETA VERSION, USE 3.124 for stable release! -* Version 3.2XX includes a all new back-end. +* Version 3.2XX includes an all new back-end. This includes automatic inlining, flattening of signals between hierarchy, and complete ordering of statements. This results in 60-300% execution speedups, though less pretty C++ output. Even @@ -3558,7 +3558,7 @@ Verilator 3.124 2003-12-05 **Major:** -* A optimized executable will be made by default, in addition to a debug +* An optimized executable will be made by default, in addition to a debug executable. Invoking Verilator with --debug will pick the debug version. **Minor:** diff --git a/README.rst b/README.rst index d46296d02..dbc308a47 100644 --- a/README.rst +++ b/README.rst @@ -29,7 +29,7 @@ Welcome to Verilator * - |verilator multithreaded performance| - **Fast** * Outperforms many closed-source commercial simulators - * Single- and multi-threaded output models + * Single- and multithreaded output models * - **Widely Used** * Wide industry and academic deployment * Out-of-the-box support from Arm, and RISC-V vendor IP @@ -52,7 +52,7 @@ What Verilator Does Verilator is invoked with parameters similar to GCC or Synopsys's VCS. It "Verilates" the specified Verilog or SystemVerilog code by reading it, performing lint checks, and optionally inserting assertion checks and -coverage-analysis points. It outputs single- or multi-threaded .cpp and .h +coverage-analysis points. It outputs single- or multithreaded .cpp and .h files, the "Verilated" code. These Verilated C++/SystemC files are then compiled by a C++ compiler @@ -61,11 +61,11 @@ file to instantiate the Verilated model. Executing the resulting executable performs the design simulation. Verilator also supports linking Verilated generated libraries, optionally encrypted, into other simulators. -Verilator may not be the best choice if you are expecting a full featured +Verilator may not be the best choice if you are expecting a full-featured replacement for a closed-source Verilog simulator, need SDF annotation, mixed-signal simulation, or are doing a quick class project (we recommend `Icarus Verilog`_ for classwork.) However, if you are looking for a path -to migrate SystemVerilog to C++/SystemC, or want high speed simulation of +to migrate SystemVerilog to C++/SystemC, or want high-speed simulation of synthesizable designs containing limited verification constructs, Verilator is the tool for you. @@ -86,7 +86,7 @@ Verilator has typically similar or better performance versus the closed-source Verilog simulators (Carbon Design Systems Carbonator, Modelsim/Questa, Cadence Incisive/NC-Verilog, Synopsys VCS, VTOC, and Pragmatic CVer/CVC). But, Verilator is open-sourced, so you can spend on -computes rather than licenses. Thus Verilator gives you the best +computes rather than licenses. Thus, Verilator gives you the best cycles/dollar. @@ -132,7 +132,7 @@ Related Projects - `GTKwave `_ - Waveform viewer for Verilator traces. -- `Icarus Verilog`_ - Icarus is a full featured interpreted Verilog +- `Icarus Verilog`_ - Icarus is a full-featured interpreted Verilog simulator. If Verilator does not support your needs, perhaps Icarus may. diff --git a/docs/CONTRIBUTING.rst b/docs/CONTRIBUTING.rst index d6cfd2fc3..15f2fed27 100644 --- a/docs/CONTRIBUTING.rst +++ b/docs/CONTRIBUTING.rst @@ -44,15 +44,10 @@ Did you write a patch that fixes a bug? - Have your patch include the addition of your name to `docs/CONTRIBUTORS `__ (preferred). - - Use "git -s" as part of your commit. This adds a "signed-of-by" - attribute which will certify your contribution as described in the - `Signed-of-By convention - `__. - - Email, or post in an issue a statement that you certify your contributions. - - In any of these cases your name will be added to `docs/CONTRIBUTORS + - In any of these cases, your name will be added to `docs/CONTRIBUTORS `__ and you are agreeing all future contributions are also certified. diff --git a/docs/guide/extensions.rst b/docs/guide/extensions.rst index c3f5c6621..24098c5ea 100644 --- a/docs/guide/extensions.rst +++ b/docs/guide/extensions.rst @@ -563,7 +563,7 @@ or "`ifdef`"'s may break other tools. .. option:: $stacktrace - Called as a task, orint a stack trace. Called as a function, return a + Called as a task, print a stack trace. Called as a function, return a string with a stack trace. This relies on the C++ system trace, which may give less meaningful results if the model was not compiled with debug symbols. Also the data represents the C++ stack, the diff --git a/docs/internals.rst b/docs/internals.rst index 3c4a2404b..f4aa386a6 100644 --- a/docs/internals.rst +++ b/docs/internals.rst @@ -42,7 +42,7 @@ The main flow of Verilator can be followed by reading the Verilator.cpp 4. Functions, variable and other references are linked to their definitions. -5. Parameters are resolved and the design is elaborated. +5. Parameters are resolved, and the design is elaborated. 6. Verilator then performs many additional edits and optimizations on the hierarchical design. This includes coverage, assertions, X @@ -149,8 +149,8 @@ an associated ``fanout``, ``color`` and ``rank``, which may be used in algorithms for ordering the graph. A generic ``user``/``userp`` member variable is also provided. -Virtual methods are provided to specify the name, color, shape and style to -be used in dot output. Typically users provide derived classes from +Virtual methods are provided to specify the name, color, shape, and style +to be used in dot output. Typically, users provide derived classes from ``V3GraphVertex`` which will reimplement these methods. Iterators are provided to access in and out edges. Typically these are used @@ -994,7 +994,7 @@ Per-Instance Classes If we have multiple instances of the same module, and they partition differently (likely; we make no attempt to partition them the same) then the variable sort will be suboptimal for either instance. A possible -improvement would be to emit a unique class for each instance of a module, +improvement would be to emit an unique class for each instance of a module, and sort its variables optimally for that instance's code stream. diff --git a/docs/spelling.txt b/docs/spelling.txt index 3e1b7e7d3..c47f7dda6 100644 --- a/docs/spelling.txt +++ b/docs/spelling.txt @@ -225,6 +225,7 @@ Nalbantis Narayan Nauticus Newgard +Nigam Nikana Niranjan Nitza @@ -239,6 +240,7 @@ Patricio Petr Piechotka Piersall +Platzer Plunkett Popolon Popov @@ -253,6 +255,7 @@ Pullup Pulver Puri Questa +Rachit Ralf Rapp Redhat @@ -383,6 +386,7 @@ agrobman ahouska al ala +alejandro algrobman andit ar @@ -407,7 +411,6 @@ biguint biops bisonpre bitOpTree -bitOpTree bitop bitstoreal blackbox @@ -422,6 +425,7 @@ callValueCbs casex casez casted +castro cb ccache ccall @@ -462,6 +466,7 @@ cutable cygwin dM da +danbone dat datadir datafiles @@ -590,6 +595,7 @@ hierCMakeArgs hierMkArgs hierVer hx +hyperthreading hyperthreads icecream idmap @@ -649,6 +655,7 @@ makefiles manpages metacomment metacomments +miree mis misconnected misconversion @@ -657,6 +664,7 @@ mk mno modport modports +mpb msg msvc mtask @@ -696,6 +704,7 @@ nullptr onehot ooo oprofile +ortegon oversubscription parallelized param @@ -748,6 +757,7 @@ pwd qrq radix randc +randcase rarr rdtsc reStructuredText diff --git a/include/verilated_cov.h b/include/verilated_cov.h index 01240f60f..bd92e064c 100644 --- a/include/verilated_cov.h +++ b/include/verilated_cov.h @@ -36,7 +36,7 @@ class VerilatedCovImp; //============================================================================= -/// Insert a item for coverage analysis. +/// Insert an item for coverage analysis. /// The first argument is a pointer to the count to be dumped. /// The remaining arguments occur in pairs: A string key, and a value. /// The value may be a string, or another type which will be auto-converted to a string. diff --git a/include/verilatedos.h b/include/verilatedos.h index 2e6e5cb49..72f80d0e7 100644 --- a/include/verilatedos.h +++ b/include/verilatedos.h @@ -387,9 +387,9 @@ using ssize_t = uint32_t; ///< signed size_t; returned from read() #define VL_BYTESIZE 8 ///< Bits in a CData / byte #define VL_SHORTSIZE 16 ///< Bits in a SData / short -#define VL_IDATASIZE 32 ///< Bits in a IData / word +#define VL_IDATASIZE 32 ///< Bits in an IData / word #define VL_QUADSIZE 64 ///< Bits in a QData / quadword -#define VL_EDATASIZE 32 ///< Bits in a EData (WData entry) +#define VL_EDATASIZE 32 ///< Bits in an EData (WData entry) #define VL_EDATASIZE_LOG2 5 ///< log2(VL_EDATASIZE) #define VL_CACHE_LINE_BYTES 64 ///< Bytes in a cache line (for alignment) @@ -443,7 +443,7 @@ using ssize_t = uint32_t; ///< signed size_t; returned from read() #define VL_BITWORD_E(bit) ((bit) >> VL_EDATASIZE_LOG2) ///< Word number for a wide quantity #define VL_BITBIT_I(bit) ((bit) & VL_SIZEBITS_I) ///< Bit number for a bit in a long #define VL_BITBIT_Q(bit) ((bit) & VL_SIZEBITS_Q) ///< Bit number for a bit in a quad -#define VL_BITBIT_E(bit) ((bit) & VL_SIZEBITS_E) ///< Bit number for a bit in a EData +#define VL_BITBIT_E(bit) ((bit) & VL_SIZEBITS_E) ///< Bit number for a bit in an EData // Return true if data[bit] set; not 0/1 return, but 0/non-zero return. #define VL_BITISSET_I(data, bit) ((data) & (VL_UL(1) << VL_BITBIT_I(bit))) diff --git a/src/.gdbinit b/src/.gdbinit index b09fa6539..9ad13ac14 100644 --- a/src/.gdbinit +++ b/src/.gdbinit @@ -31,5 +31,5 @@ define watchedit watch AstNode::s_editCntGbl==$arg0 end document watchedit - Verilator: Create watch on where a edit number is made + Verilator: Create watch on where an edit number is made end diff --git a/src/V3AstNodeExpr.h b/src/V3AstNodeExpr.h index da8683b5c..5b2bb9d43 100644 --- a/src/V3AstNodeExpr.h +++ b/src/V3AstNodeExpr.h @@ -312,7 +312,7 @@ public: bool same(const AstNode*) const override { return true; } }; class AstNodeTermop VL_NOT_FINAL : public AstNodeExpr { - // Terminal operator -- a operator with no "inputs" + // Terminal operator -- an operator with no "inputs" protected: AstNodeTermop(VNType t, FileLine* fl) : AstNodeExpr{t, fl} {} diff --git a/src/V3AstNodeOther.h b/src/V3AstNodeOther.h index 74a14a238..e407dbf4a 100644 --- a/src/V3AstNodeOther.h +++ b/src/V3AstNodeOther.h @@ -2231,7 +2231,7 @@ public: // === AstNodeRange === class AstBracketRange final : public AstNodeRange { - // Parser only concept "[lhsp]", a AstUnknownRange, QueueRange or Range, + // Parser only concept "[lhsp]", an AstUnknownRange, QueueRange or Range, // unknown until lhsp type is determined // @astgen op1 := elementsp : AstNode // Expr or DType public: diff --git a/src/V3Gate.cpp b/src/V3Gate.cpp index ead1d325f..fe8fae672 100644 --- a/src/V3Gate.cpp +++ b/src/V3Gate.cpp @@ -283,7 +283,7 @@ public: for (GateVarRefList::const_iterator it = m_rhsVarRefs.begin(); it != m_rhsVarRefs.end(); ++it) { if (m_lhsVarRef && m_lhsVarRef->varScopep() == (*it)->varScopep()) { - clearSimple("Circular logic\n"); // Oh my, we'll get a UNOPTFLAT much later. + clearSimple("Circular logic\n"); // Oh my, we'll get an UNOPTFLAT much later } } if (debug() >= 9 && !m_isSimple) nodep->dumpTree("- gate!Ok: "); diff --git a/src/V3Graph.h b/src/V3Graph.h index e54e5d46c..8589a003c 100644 --- a/src/V3Graph.h +++ b/src/V3Graph.h @@ -115,7 +115,7 @@ public: /// (I.E. all loops will occur within each color, not between them.) void stronglyConnected(V3EdgeFuncP edgeFuncp); - /// Assign a ordering number to all vertexes in a tree. + /// Assign an ordering number to all vertexes in a tree. /// All nodes with no inputs will get rank 1 void rank(V3EdgeFuncP edgeFuncp); void rank(); diff --git a/src/V3List.h b/src/V3List.h index e7e524c6e..c32794cc2 100644 --- a/src/V3List.h +++ b/src/V3List.h @@ -64,7 +64,7 @@ private: T m_prevp = nullptr; // Pointer to previous element, nullptr=beginning friend class V3List; static V3ListEnt* baseToListEnt(void* newbasep, size_t offset) { - // "this" must be a element inside of *basep + // "this" must be an element inside of *basep // Use that to determine a structure offset, then apply to the new base // to get our new pointer information return (V3ListEnt*)(((uint8_t*)newbasep) + offset); @@ -83,7 +83,7 @@ public: T prevp() const { return m_prevp; } // METHODS void pushBack(V3List& listr, T newp) { - // "this" must be a element inside of *newp + // "this" must be an element inside of *newp // cppcheck-suppress thisSubtraction const size_t offset = (size_t)(uint8_t*)(this) - (size_t)(uint8_t*)(newp); m_nextp = nullptr; @@ -93,7 +93,7 @@ public: listr.m_tailp = newp; } void pushFront(V3List& listr, T newp) { - // "this" must be a element inside of *newp + // "this" must be an element inside of *newp // cppcheck-suppress thisSubtraction const size_t offset = (size_t)(uint8_t*)(this) - (size_t)(uint8_t*)(newp); m_nextp = listr.m_headp; @@ -104,7 +104,7 @@ public: } // Unlink from side void unlink(V3List& listr, T oldp) { - // "this" must be a element inside of *oldp + // "this" must be an element inside of *oldp // cppcheck-suppress thisSubtraction const size_t offset = (size_t)(uint8_t*)(this) - (size_t)(uint8_t*)(oldp); if (m_nextp) { diff --git a/src/V3OptionParser.cpp b/src/V3OptionParser.cpp index cc019b33d..7c26d1a86 100644 --- a/src/V3OptionParser.cpp +++ b/src/V3OptionParser.cpp @@ -74,7 +74,7 @@ struct V3OptionParser::Impl { #define V3OPTION_PARSER_DEF_ACT_CLASS(className, type, body, enType) \ template <> \ class V3OptionParser::Impl::className final : public ActionBase { \ - type* const m_valp; /* Pointer to a option variable*/ \ + type* const m_valp; /* Pointer to an option variable*/ \ \ public: \ explicit className(type* valp) \ diff --git a/src/verilog.y b/src/verilog.y index 8621e4e6b..311e68a4c 100644 --- a/src/verilog.y +++ b/src/verilog.y @@ -991,9 +991,9 @@ BISONPRE_VERSION(3.7,%define api.header.include {"V3ParseBison.h"}) %token yP_SRIGHTEQ ">>=" %token yP_SSRIGHTEQ ">>>=" -// [* is not a operator, as "[ * ]" is legal +// [* is not an operator, as "[ * ]" is legal // [= and [-> could be repitition operators, but to match [* we don't add them. -// '( is not a operator, as "' (" is legal +// '( is not an operator, as "' (" is legal //******************** // Verilog op precedence diff --git a/test_regress/driver.pl b/test_regress/driver.pl index 03018ac01..a2a7899a1 100755 --- a/test_regress/driver.pl +++ b/test_regress/driver.pl @@ -1575,7 +1575,7 @@ sub _run { if ($param{verilator_run}) { # Gcov fails when parallel jobs write same data file, # so we make sure .gcda output dir is unique across all running jobs. - # We can't just put each one in a unique obj_dir as it uses too much disk. + # We can't just put each one in an unique obj_dir as it uses too much disk. # Must use absolute path as some execute()s have different PWD $ENV{GCOV_PREFIX_STRIP} = 99; $ENV{GCOV_PREFIX} = File::Spec->rel2abs("$FindBin::RealBin/obj_dist/gcov_$self->{running_id}"); diff --git a/test_regress/t/t_extend_class_c.h b/test_regress/t/t_extend_class_c.h index a1cdd58dc..d1bd62610 100644 --- a/test_regress/t/t_extend_class_c.h +++ b/test_regress/t/t_extend_class_c.h @@ -12,6 +12,6 @@ public: t_extend_class_c() = default; ~t_extend_class_c() = default; // METHODS - // This function will be called from a instance created in Verilog + // This function will be called from an instance created in Verilog uint32_t my_math(uint32_t in) { return in + 1; } };