Fix 0**0 with wide numbers (#4721).

This commit is contained in:
Wilson Snyder 2023-11-26 17:11:22 -05:00
parent a7a48221d3
commit a022b672a0
7 changed files with 780 additions and 67 deletions

View File

@ -35,6 +35,7 @@ Verilator 5.019 devel
* Fix trace when using SystemC with certain configurations (#4676). [Anthony Donlon]
* Fix C++20 compilation errors (#4670).
* Fix compilers seeing empty input due to file system races (#4708). [Flavien Solt]
* Fix 0**0 with wide numbers (#4721). [Flavien Solt]
Verilator 5.018 2023-10-30

View File

@ -576,7 +576,10 @@ WDataOutP VL_POW_WWQ(int obits, int lbits, int rbits, WDataOutP owp, const WData
return VL_POW_WWW(obits, lbits, rbits, owp, lwp, rhsw);
}
QData VL_POW_QQW(int, int, int rbits, QData lhs, const WDataInP rwp) VL_MT_SAFE {
// Skip check for rhs == 0, as short-circuit doesn't save time
const int rwords = VL_WORDS_I(rbits);
EData rnz = rwp[0];
for (int w = 1; w < rwords; ++w) rnz |= rwp[w];
if (!rnz) return 1; // rwp == 0
if (VL_UNLIKELY(lhs == 0)) return 0;
QData power = lhs;
QData result = 1ULL;

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@ -0,0 +1,433 @@
gold: u 7ffffffffffffffff**7ffffffffffffffff: uiii = ffff
gold: u 7ffffffffffffffff**7ffffffffffffffff: uiiq = ffff
gold: u 7ffffffffffffffff**7ffffffffffffffff: uiiw = ffff
gold: u 7ffffffffffffffff**7ffffffffffffffff: uiqi = ffff
gold: u 7ffffffffffffffff**7ffffffffffffffff: uiqq = ffff
gold: u 7ffffffffffffffff**7ffffffffffffffff: uiqw = ffff
gold: u 7ffffffffffffffff**7ffffffffffffffff: uiwi = ffff
gold: u 7ffffffffffffffff**7ffffffffffffffff: uiwq = ffff
gold: u 7ffffffffffffffff**7ffffffffffffffff: uiww = ffff
gold: u 7ffffffffffffffff**7ffffffffffffffff: uqii = 7fffeffff
gold: u 7ffffffffffffffff**7ffffffffffffffff: uqiq = 6fffeffff
gold: u 7ffffffffffffffff**7ffffffffffffffff: uqiw = 6fffeffff
gold: u 7ffffffffffffffff**7ffffffffffffffff: uqqi = 7ffffffff
gold: u 7ffffffffffffffff**7ffffffffffffffff: uqqq = 7ffffffff
gold: u 7ffffffffffffffff**7ffffffffffffffff: uqqw = 7ffffffff
gold: u 7ffffffffffffffff**7ffffffffffffffff: uqwi = 7ffffffff
gold: u 7ffffffffffffffff**7ffffffffffffffff: uqwq = 7ffffffff
gold: u 7ffffffffffffffff**7ffffffffffffffff: uqww = 7ffffffff
gold: u 7ffffffffffffffff**7ffffffffffffffff: uwii = 300007ffffffeffff
gold: u 7ffffffffffffffff**7ffffffffffffffff: uwiq = 30006fffefffeffff
gold: u 7ffffffffffffffff**7ffffffffffffffff: uwiw = 6fffefffefffeffff
gold: u 7ffffffffffffffff**7ffffffffffffffff: uwqi = 7fff7ffffffff
gold: u 7ffffffffffffffff**7ffffffffffffffff: uwqq = 7fffffff7ffffffff
gold: u 7ffffffffffffffff**7ffffffffffffffff: uwqw = 7fffffff7ffffffff
gold: u 7ffffffffffffffff**7ffffffffffffffff: uwwi = 7ffffffffffffffff
gold: u 7ffffffffffffffff**7ffffffffffffffff: uwwq = 7ffffffffffffffff
gold: u 7ffffffffffffffff**7ffffffffffffffff: uwww = 7ffffffffffffffff
gold: s -1**-1: siii = -1
gold: s -1**-1: siiq = -1
gold: s -1**-1: siiw = -1
gold: s -1**-1: siqi = -1
gold: s -1**-1: siqq = -1
gold: s -1**-1: siqw = -1
gold: s -1**-1: siwi = -1
gold: s -1**-1: siwq = -1
gold: s -1**-1: siww = -1
gold: s -1**-1: sqii = -1
gold: s -1**-1: sqiq = -1
gold: s -1**-1: sqiw = -1
gold: s -1**-1: sqqi = -1
gold: s -1**-1: sqqq = -1
gold: s -1**-1: sqqw = -1
gold: s -1**-1: sqwi = -1
gold: s -1**-1: sqwq = -1
gold: s -1**-1: sqww = -1
gold: s -1**-1: swii = -1
gold: s -1**-1: swiq = -1
gold: s -1**-1: swiw = -1
gold: s -1**-1: swqi = -1
gold: s -1**-1: swqq = -1
gold: s -1**-1: swqw = -1
gold: s -1**-1: swwi = -1
gold: s -1**-1: swwq = -1
gold: s -1**-1: swww = -1
gold: u 7ffffffffffffffff**2: uiii = 1
gold: u 7ffffffffffffffff**2: uiiq = 1
gold: u 7ffffffffffffffff**2: uiiw = 1
gold: u 7ffffffffffffffff**2: uiqi = 1
gold: u 7ffffffffffffffff**2: uiqq = 1
gold: u 7ffffffffffffffff**2: uiqw = 1
gold: u 7ffffffffffffffff**2: uiwi = 1
gold: u 7ffffffffffffffff**2: uiwq = 1
gold: u 7ffffffffffffffff**2: uiww = 1
gold: u 7ffffffffffffffff**2: uqii = fffe0001
gold: u 7ffffffffffffffff**2: uqiq = fffe0001
gold: u 7ffffffffffffffff**2: uqiw = fffe0001
gold: u 7ffffffffffffffff**2: uqqi = 1
gold: u 7ffffffffffffffff**2: uqqq = 1
gold: u 7ffffffffffffffff**2: uqqw = 1
gold: u 7ffffffffffffffff**2: uqwi = 1
gold: u 7ffffffffffffffff**2: uqwq = 1
gold: u 7ffffffffffffffff**2: uqww = 1
gold: u 7ffffffffffffffff**2: uwii = fffe0001
gold: u 7ffffffffffffffff**2: uwiq = fffe0001
gold: u 7ffffffffffffffff**2: uwiw = fffe0001
gold: u 7ffffffffffffffff**2: uwqi = 7fffffff000000001
gold: u 7ffffffffffffffff**2: uwqq = 7fffffff000000001
gold: u 7ffffffffffffffff**2: uwqw = 7fffffff000000001
gold: u 7ffffffffffffffff**2: uwwi = 1
gold: u 7ffffffffffffffff**2: uwwq = 1
gold: u 7ffffffffffffffff**2: uwww = 1
gold: s -1**2: siii = 1
gold: s -1**2: siiq = 1
gold: s -1**2: siiw = 1
gold: s -1**2: siqi = 1
gold: s -1**2: siqq = 1
gold: s -1**2: siqw = 1
gold: s -1**2: siwi = 1
gold: s -1**2: siwq = 1
gold: s -1**2: siww = 1
gold: s -1**2: sqii = 1
gold: s -1**2: sqiq = 1
gold: s -1**2: sqiw = 1
gold: s -1**2: sqqi = 1
gold: s -1**2: sqqq = 1
gold: s -1**2: sqqw = 1
gold: s -1**2: sqwi = 1
gold: s -1**2: sqwq = 1
gold: s -1**2: sqww = 1
gold: s -1**2: swii = 1
gold: s -1**2: swiq = 1
gold: s -1**2: swiw = 1
gold: s -1**2: swqi = 1
gold: s -1**2: swqq = 1
gold: s -1**2: swqw = 1
gold: s -1**2: swwi = 1
gold: s -1**2: swwq = 1
gold: s -1**2: swww = 1
gold: u 7ffffffffffffffff**3: uiii = ffff
gold: u 7ffffffffffffffff**3: uiiq = ffff
gold: u 7ffffffffffffffff**3: uiiw = ffff
gold: u 7ffffffffffffffff**3: uiqi = ffff
gold: u 7ffffffffffffffff**3: uiqq = ffff
gold: u 7ffffffffffffffff**3: uiqw = ffff
gold: u 7ffffffffffffffff**3: uiwi = ffff
gold: u 7ffffffffffffffff**3: uiwq = ffff
gold: u 7ffffffffffffffff**3: uiww = ffff
gold: u 7ffffffffffffffff**3: uqii = 50002ffff
gold: u 7ffffffffffffffff**3: uqiq = 50002ffff
gold: u 7ffffffffffffffff**3: uqiw = 50002ffff
gold: u 7ffffffffffffffff**3: uqqi = 7ffffffff
gold: u 7ffffffffffffffff**3: uqqq = 7ffffffff
gold: u 7ffffffffffffffff**3: uqqw = 7ffffffff
gold: u 7ffffffffffffffff**3: uqwi = 7ffffffff
gold: u 7ffffffffffffffff**3: uqwq = 7ffffffff
gold: u 7ffffffffffffffff**3: uqww = 7ffffffff
gold: u 7ffffffffffffffff**3: uwii = fffd0002ffff
gold: u 7ffffffffffffffff**3: uwiq = fffd0002ffff
gold: u 7ffffffffffffffff**3: uwiw = fffd0002ffff
gold: u 7ffffffffffffffff**3: uwqi = 17ffffffff
gold: u 7ffffffffffffffff**3: uwqq = 17ffffffff
gold: u 7ffffffffffffffff**3: uwqw = 17ffffffff
gold: u 7ffffffffffffffff**3: uwwi = 7ffffffffffffffff
gold: u 7ffffffffffffffff**3: uwwq = 7ffffffffffffffff
gold: u 7ffffffffffffffff**3: uwww = 7ffffffffffffffff
gold: s -1**3: siii = -1
gold: s -1**3: siiq = -1
gold: s -1**3: siiw = -1
gold: s -1**3: siqi = -1
gold: s -1**3: siqq = -1
gold: s -1**3: siqw = -1
gold: s -1**3: siwi = -1
gold: s -1**3: siwq = -1
gold: s -1**3: siww = -1
gold: s -1**3: sqii = -1
gold: s -1**3: sqiq = -1
gold: s -1**3: sqiw = -1
gold: s -1**3: sqqi = -1
gold: s -1**3: sqqq = -1
gold: s -1**3: sqqw = -1
gold: s -1**3: sqwi = -1
gold: s -1**3: sqwq = -1
gold: s -1**3: sqww = -1
gold: s -1**3: swii = -1
gold: s -1**3: swiq = -1
gold: s -1**3: swiw = -1
gold: s -1**3: swqi = -1
gold: s -1**3: swqq = -1
gold: s -1**3: swqw = -1
gold: s -1**3: swwi = -1
gold: s -1**3: swwq = -1
gold: s -1**3: swww = -1
gold: u 3**7ffffffffffffffff: uiii = aaab
gold: u 3**7ffffffffffffffff: uiiq = aaab
gold: u 3**7ffffffffffffffff: uiiw = aaab
gold: u 3**7ffffffffffffffff: uiqi = aaab
gold: u 3**7ffffffffffffffff: uiqq = aaab
gold: u 3**7ffffffffffffffff: uiqw = aaab
gold: u 3**7ffffffffffffffff: uiwi = aaab
gold: u 3**7ffffffffffffffff: uiwq = aaab
gold: u 3**7ffffffffffffffff: uiww = aaab
gold: u 3**7ffffffffffffffff: uqii = 64da6aaab
gold: u 3**7ffffffffffffffff: uqiq = 2aaaaaaab
gold: u 3**7ffffffffffffffff: uqiw = 2aaaaaaab
gold: u 3**7ffffffffffffffff: uqqi = 64da6aaab
gold: u 3**7ffffffffffffffff: uqqq = 2aaaaaaab
gold: u 3**7ffffffffffffffff: uqqw = 2aaaaaaab
gold: u 3**7ffffffffffffffff: uqwi = 64da6aaab
gold: u 3**7ffffffffffffffff: uqwq = 2aaaaaaab
gold: u 3**7ffffffffffffffff: uqww = 2aaaaaaab
gold: u 3**7ffffffffffffffff: uwii = 78fa2e79e4da6aaab
gold: u 3**7ffffffffffffffff: uwiq = 5b187c28aaaaaaaab
gold: u 3**7ffffffffffffffff: uwiw = 2aaaaaaaaaaaaaaab
gold: u 3**7ffffffffffffffff: uwqi = 78fa2e79e4da6aaab
gold: u 3**7ffffffffffffffff: uwqq = 5b187c28aaaaaaaab
gold: u 3**7ffffffffffffffff: uwqw = 2aaaaaaaaaaaaaaab
gold: u 3**7ffffffffffffffff: uwwi = 78fa2e79e4da6aaab
gold: u 3**7ffffffffffffffff: uwwq = 5b187c28aaaaaaaab
gold: u 3**7ffffffffffffffff: uwww = 2aaaaaaaaaaaaaaab
gold: s 3**-1: siii = 0
gold: s 3**-1: siiq = 0
gold: s 3**-1: siiw = 0
gold: s 3**-1: siqi = 0
gold: s 3**-1: siqq = 0
gold: s 3**-1: siqw = 0
gold: s 3**-1: siwi = 0
gold: s 3**-1: siwq = 0
gold: s 3**-1: siww = 0
gold: s 3**-1: sqii = 0
gold: s 3**-1: sqiq = 0
gold: s 3**-1: sqiw = 0
gold: s 3**-1: sqqi = 0
gold: s 3**-1: sqqq = 0
gold: s 3**-1: sqqw = 0
gold: s 3**-1: sqwi = 0
gold: s 3**-1: sqwq = 0
gold: s 3**-1: sqww = 0
gold: s 3**-1: swii = 0
gold: s 3**-1: swiq = 0
gold: s 3**-1: swiw = 0
gold: s 3**-1: swqi = 0
gold: s 3**-1: swqq = 0
gold: s 3**-1: swqw = 0
gold: s 3**-1: swwi = 0
gold: s 3**-1: swwq = 0
gold: s 3**-1: swww = 0
gold: u 7fffffffffffffffe**1: uiii = fffe
gold: u 7fffffffffffffffe**1: uiiq = fffe
gold: u 7fffffffffffffffe**1: uiiw = fffe
gold: u 7fffffffffffffffe**1: uiqi = fffe
gold: u 7fffffffffffffffe**1: uiqq = fffe
gold: u 7fffffffffffffffe**1: uiqw = fffe
gold: u 7fffffffffffffffe**1: uiwi = fffe
gold: u 7fffffffffffffffe**1: uiwq = fffe
gold: u 7fffffffffffffffe**1: uiww = fffe
gold: u 7fffffffffffffffe**1: uqii = fffe
gold: u 7fffffffffffffffe**1: uqiq = fffe
gold: u 7fffffffffffffffe**1: uqiw = fffe
gold: u 7fffffffffffffffe**1: uqqi = 7fffffffe
gold: u 7fffffffffffffffe**1: uqqq = 7fffffffe
gold: u 7fffffffffffffffe**1: uqqw = 7fffffffe
gold: u 7fffffffffffffffe**1: uqwi = 7fffffffe
gold: u 7fffffffffffffffe**1: uqwq = 7fffffffe
gold: u 7fffffffffffffffe**1: uqww = 7fffffffe
gold: u 7fffffffffffffffe**1: uwii = fffe
gold: u 7fffffffffffffffe**1: uwiq = fffe
gold: u 7fffffffffffffffe**1: uwiw = fffe
gold: u 7fffffffffffffffe**1: uwqi = 7fffffffe
gold: u 7fffffffffffffffe**1: uwqq = 7fffffffe
gold: u 7fffffffffffffffe**1: uwqw = 7fffffffe
gold: u 7fffffffffffffffe**1: uwwi = 7fffffffffffffffe
gold: u 7fffffffffffffffe**1: uwwq = 7fffffffffffffffe
gold: u 7fffffffffffffffe**1: uwww = 7fffffffffffffffe
gold: s -2**1: siii = -2
gold: s -2**1: siiq = -2
gold: s -2**1: siiw = -2
gold: s -2**1: siqi = -2
gold: s -2**1: siqq = -2
gold: s -2**1: siqw = -2
gold: s -2**1: siwi = -2
gold: s -2**1: siwq = -2
gold: s -2**1: siww = -2
gold: s -2**1: sqii = -2
gold: s -2**1: sqiq = -2
gold: s -2**1: sqiw = -2
gold: s -2**1: sqqi = -2
gold: s -2**1: sqqq = -2
gold: s -2**1: sqqw = -2
gold: s -2**1: sqwi = -2
gold: s -2**1: sqwq = -2
gold: s -2**1: sqww = -2
gold: s -2**1: swii = -2
gold: s -2**1: swiq = -2
gold: s -2**1: swiw = -2
gold: s -2**1: swqi = -2
gold: s -2**1: swqq = -2
gold: s -2**1: swqw = -2
gold: s -2**1: swwi = -2
gold: s -2**1: swwq = -2
gold: s -2**1: swww = -2
gold: u 7fffffffffffffffe**7ffffffffffffffff: uiii = 0
gold: u 7fffffffffffffffe**7ffffffffffffffff: uiiq = 0
gold: u 7fffffffffffffffe**7ffffffffffffffff: uiiw = 0
gold: u 7fffffffffffffffe**7ffffffffffffffff: uiqi = 0
gold: u 7fffffffffffffffe**7ffffffffffffffff: uiqq = 0
gold: u 7fffffffffffffffe**7ffffffffffffffff: uiqw = 0
gold: u 7fffffffffffffffe**7ffffffffffffffff: uiwi = 0
gold: u 7fffffffffffffffe**7ffffffffffffffff: uiwq = 0
gold: u 7fffffffffffffffe**7ffffffffffffffff: uiww = 0
gold: u 7fffffffffffffffe**7ffffffffffffffff: uqii = 0
gold: u 7fffffffffffffffe**7ffffffffffffffff: uqiq = 0
gold: u 7fffffffffffffffe**7ffffffffffffffff: uqiw = 0
gold: u 7fffffffffffffffe**7ffffffffffffffff: uqqi = 0
gold: u 7fffffffffffffffe**7ffffffffffffffff: uqqq = 0
gold: u 7fffffffffffffffe**7ffffffffffffffff: uqqw = 0
gold: u 7fffffffffffffffe**7ffffffffffffffff: uqwi = 0
gold: u 7fffffffffffffffe**7ffffffffffffffff: uqwq = 0
gold: u 7fffffffffffffffe**7ffffffffffffffff: uqww = 0
gold: u 7fffffffffffffffe**7ffffffffffffffff: uwii = 0
gold: u 7fffffffffffffffe**7ffffffffffffffff: uwiq = 0
gold: u 7fffffffffffffffe**7ffffffffffffffff: uwiw = 0
gold: u 7fffffffffffffffe**7ffffffffffffffff: uwqi = 0
gold: u 7fffffffffffffffe**7ffffffffffffffff: uwqq = 0
gold: u 7fffffffffffffffe**7ffffffffffffffff: uwqw = 0
gold: u 7fffffffffffffffe**7ffffffffffffffff: uwwi = 0
gold: u 7fffffffffffffffe**7ffffffffffffffff: uwwq = 0
gold: u 7fffffffffffffffe**7ffffffffffffffff: uwww = 0
gold: s -2**-1: siii = 0
gold: s -2**-1: siiq = 0
gold: s -2**-1: siiw = 0
gold: s -2**-1: siqi = 0
gold: s -2**-1: siqq = 0
gold: s -2**-1: siqw = 0
gold: s -2**-1: siwi = 0
gold: s -2**-1: siwq = 0
gold: s -2**-1: siww = 0
gold: s -2**-1: sqii = 0
gold: s -2**-1: sqiq = 0
gold: s -2**-1: sqiw = 0
gold: s -2**-1: sqqi = 0
gold: s -2**-1: sqqq = 0
gold: s -2**-1: sqqw = 0
gold: s -2**-1: sqwi = 0
gold: s -2**-1: sqwq = 0
gold: s -2**-1: sqww = 0
gold: s -2**-1: swii = 0
gold: s -2**-1: swiq = 0
gold: s -2**-1: swiw = 0
gold: s -2**-1: swqi = 0
gold: s -2**-1: swqq = 0
gold: s -2**-1: swqw = 0
gold: s -2**-1: swwi = 0
gold: s -2**-1: swwq = 0
gold: s -2**-1: swww = 0
gold: u 7fffffffffffffffe**2: uiii = 4
gold: u 7fffffffffffffffe**2: uiiq = 4
gold: u 7fffffffffffffffe**2: uiiw = 4
gold: u 7fffffffffffffffe**2: uiqi = 4
gold: u 7fffffffffffffffe**2: uiqq = 4
gold: u 7fffffffffffffffe**2: uiqw = 4
gold: u 7fffffffffffffffe**2: uiwi = 4
gold: u 7fffffffffffffffe**2: uiwq = 4
gold: u 7fffffffffffffffe**2: uiww = 4
gold: u 7fffffffffffffffe**2: uqii = fffc0004
gold: u 7fffffffffffffffe**2: uqiq = fffc0004
gold: u 7fffffffffffffffe**2: uqiw = fffc0004
gold: u 7fffffffffffffffe**2: uqqi = 4
gold: u 7fffffffffffffffe**2: uqqq = 4
gold: u 7fffffffffffffffe**2: uqqw = 4
gold: u 7fffffffffffffffe**2: uqwi = 4
gold: u 7fffffffffffffffe**2: uqwq = 4
gold: u 7fffffffffffffffe**2: uqww = 4
gold: u 7fffffffffffffffe**2: uwii = fffc0004
gold: u 7fffffffffffffffe**2: uwiq = fffc0004
gold: u 7fffffffffffffffe**2: uwiw = fffc0004
gold: u 7fffffffffffffffe**2: uwqi = 7ffffffe000000004
gold: u 7fffffffffffffffe**2: uwqq = 7ffffffe000000004
gold: u 7fffffffffffffffe**2: uwqw = 7ffffffe000000004
gold: u 7fffffffffffffffe**2: uwwi = 4
gold: u 7fffffffffffffffe**2: uwwq = 4
gold: u 7fffffffffffffffe**2: uwww = 4
gold: s -2**2: siii = 4
gold: s -2**2: siiq = 4
gold: s -2**2: siiw = 4
gold: s -2**2: siqi = 4
gold: s -2**2: siqq = 4
gold: s -2**2: siqw = 4
gold: s -2**2: siwi = 4
gold: s -2**2: siwq = 4
gold: s -2**2: siww = 4
gold: s -2**2: sqii = 4
gold: s -2**2: sqiq = 4
gold: s -2**2: sqiw = 4
gold: s -2**2: sqqi = 4
gold: s -2**2: sqqq = 4
gold: s -2**2: sqqw = 4
gold: s -2**2: sqwi = 4
gold: s -2**2: sqwq = 4
gold: s -2**2: sqww = 4
gold: s -2**2: swii = 4
gold: s -2**2: swiq = 4
gold: s -2**2: swiw = 4
gold: s -2**2: swqi = 4
gold: s -2**2: swqq = 4
gold: s -2**2: swqw = 4
gold: s -2**2: swwi = 4
gold: s -2**2: swwq = 4
gold: s -2**2: swww = 4
gold: u 7fffffffffffffffe**3: uiii = fff8
gold: u 7fffffffffffffffe**3: uiiq = fff8
gold: u 7fffffffffffffffe**3: uiiw = fff8
gold: u 7fffffffffffffffe**3: uiqi = fff8
gold: u 7fffffffffffffffe**3: uiqq = fff8
gold: u 7fffffffffffffffe**3: uiqw = fff8
gold: u 7fffffffffffffffe**3: uiwi = fff8
gold: u 7fffffffffffffffe**3: uiwq = fff8
gold: u 7fffffffffffffffe**3: uiww = fff8
gold: u 7fffffffffffffffe**3: uqii = 2000bfff8
gold: u 7fffffffffffffffe**3: uqiq = 2000bfff8
gold: u 7fffffffffffffffe**3: uqiw = 2000bfff8
gold: u 7fffffffffffffffe**3: uqqi = 7fffffff8
gold: u 7fffffffffffffffe**3: uqqq = 7fffffff8
gold: u 7fffffffffffffffe**3: uqqw = 7fffffff8
gold: u 7fffffffffffffffe**3: uqwi = 7fffffff8
gold: u 7fffffffffffffffe**3: uqwq = 7fffffff8
gold: u 7fffffffffffffffe**3: uqww = 7fffffff8
gold: u 7fffffffffffffffe**3: uwii = fffa000bfff8
gold: u 7fffffffffffffffe**3: uwiq = fffa000bfff8
gold: u 7fffffffffffffffe**3: uwiw = fffa000bfff8
gold: u 7fffffffffffffffe**3: uwqi = 5ffffffff8
gold: u 7fffffffffffffffe**3: uwqq = 5ffffffff8
gold: u 7fffffffffffffffe**3: uwqw = 5ffffffff8
gold: u 7fffffffffffffffe**3: uwwi = 7fffffffffffffff8
gold: u 7fffffffffffffffe**3: uwwq = 7fffffffffffffff8
gold: u 7fffffffffffffffe**3: uwww = 7fffffffffffffff8
gold: s -2**3: siii = -8
gold: s -2**3: siiq = -8
gold: s -2**3: siiw = -8
gold: s -2**3: siqi = -8
gold: s -2**3: siqq = -8
gold: s -2**3: siqw = -8
gold: s -2**3: siwi = -8
gold: s -2**3: siwq = -8
gold: s -2**3: siww = -8
gold: s -2**3: sqii = -8
gold: s -2**3: sqiq = -8
gold: s -2**3: sqiw = -8
gold: s -2**3: sqqi = -8
gold: s -2**3: sqqq = -8
gold: s -2**3: sqqw = -8
gold: s -2**3: sqwi = -8
gold: s -2**3: sqwq = -8
gold: s -2**3: sqww = -8
gold: s -2**3: swii = -8
gold: s -2**3: swiq = -8
gold: s -2**3: swiw = -8
gold: s -2**3: swqi = -8
gold: s -2**3: swqq = -8
gold: s -2**3: swqw = -8
gold: s -2**3: swwi = -8
gold: s -2**3: swwq = -8
gold: s -2**3: swww = -8
*-* All Finished *-*

View File

@ -11,11 +11,35 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
scenarios(simulator => 1);
compile(
verilator_flags2 => ['-fno-gate'],
);
execute(
check_finished => 1,
expect_filename => $Self->{golden_filename},
);
# Check for coverage on all POW functions
system("cat $Self->{obj_dir}/$Self->{vm_prefix}_*.cpp > $Self->{obj_dir}/all.cpp");
file_grep("$Self->{obj_dir}/all.cpp", qr/VL_POW_III/);
file_grep("$Self->{obj_dir}/all.cpp", qr/VL_POW_IIQ/);
file_grep("$Self->{obj_dir}/all.cpp", qr/VL_POW_IIW/);
file_grep("$Self->{obj_dir}/all.cpp", qr/VL_POW_QQI/);
file_grep("$Self->{obj_dir}/all.cpp", qr/VL_POW_QQQ/);
file_grep("$Self->{obj_dir}/all.cpp", qr/VL_POW_QQW/);
file_grep("$Self->{obj_dir}/all.cpp", qr/VL_POW_WWI/);
file_grep("$Self->{obj_dir}/all.cpp", qr/VL_POW_WWQ/);
file_grep("$Self->{obj_dir}/all.cpp", qr/VL_POW_WWW/);
file_grep("$Self->{obj_dir}/all.cpp", qr/VL_POWSS_III/);
file_grep("$Self->{obj_dir}/all.cpp", qr/VL_POWSS_IIQ/);
file_grep("$Self->{obj_dir}/all.cpp", qr/VL_POWSS_IIW/);
file_grep("$Self->{obj_dir}/all.cpp", qr/VL_POWSS_QQI/);
file_grep("$Self->{obj_dir}/all.cpp", qr/VL_POWSS_QQQ/);
file_grep("$Self->{obj_dir}/all.cpp", qr/VL_POWSS_QQW/);
file_grep("$Self->{obj_dir}/all.cpp", qr/VL_POWSS_WWI/);
file_grep("$Self->{obj_dir}/all.cpp", qr/VL_POWSS_WWQ/);
file_grep("$Self->{obj_dir}/all.cpp", qr/VL_POWSS_WWW/);
ok(1);
1;

View File

@ -4,8 +4,11 @@
// any use, without warranty, 2005 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
`define STRINGIFY(x) `"x`"
`define stop $stop
`ifdef VERILATOR
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0)
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0)
`else
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); end while(0)
`endif
@ -17,89 +20,338 @@ module t (/*AUTOARG*/
input clk;
reg [60:0] p;
reg [60:0] a;
reg [20:0] b;
reg [60:0] shifted;
reg [66:0] a;
reg [66:0] b;
always @* begin
p = a[60:0] ** b[20:0];
shifted = 2 ** b[20:0];
end
wire [15:0] aui = a[15:0];
wire [34:0] auq = a[34:0];
wire [66:0] auw = a[66:0];
wire [15:0] bui = b[15:0];
wire [34:0] buq = b[34:0];
wire [66:0] buw = b[66:0];
wire signed [15:0] asi = a[15:0];
wire signed [34:0] asq = a[34:0];
wire signed [66:0] asw = a[66:0];
wire signed [15:0] bsi = b[15:0];
wire signed [34:0] bsq = b[34:0];
wire signed [66:0] bsw = b[66:0];
// verilator lint_off WIDTH
wire [66:0] shifted = 2 ** b[20:0];
wire [15:0] uiii = aui ** bui;
wire [15:0] uiiq = aui ** buq;
wire [15:0] uiiw = aui ** buw;
wire [15:0] uiqi = auq ** bui;
wire [15:0] uiqq = auq ** buq;
wire [15:0] uiqw = auq ** buw;
wire [15:0] uiwi = auw ** bui;
wire [15:0] uiwq = auw ** buq;
wire [15:0] uiww = auw ** buw;
wire [34:0] uqii = aui ** bui;
wire [34:0] uqiq = aui ** buq;
wire [34:0] uqiw = aui ** buw;
wire [34:0] uqqi = auq ** bui;
wire [34:0] uqqq = auq ** buq;
wire [34:0] uqqw = auq ** buw;
wire [34:0] uqwi = auw ** bui;
wire [34:0] uqwq = auw ** buq;
wire [34:0] uqww = auw ** buw;
wire [66:0] uwii = aui ** bui;
wire [66:0] uwiq = aui ** buq;
wire [66:0] uwiw = aui ** buw;
wire [66:0] uwqi = auq ** bui;
wire [66:0] uwqq = auq ** buq;
wire [66:0] uwqw = auq ** buw;
wire [66:0] uwwi = auw ** bui;
wire [66:0] uwwq = auw ** buq;
wire [66:0] uwww = auw ** buw;
wire signed [15:0] siii = asi ** bsi;
wire signed [15:0] siiq = asi ** bsq;
wire signed [15:0] siiw = asi ** bsw;
wire signed [15:0] siqi = asq ** bsi;
wire signed [15:0] siqq = asq ** bsq;
wire signed [15:0] siqw = asq ** bsw;
wire signed [15:0] siwi = asw ** bsi;
wire signed [15:0] siwq = asw ** bsq;
wire signed [15:0] siww = asw ** bsw;
wire signed [34:0] sqii = asi ** bsi;
wire signed [34:0] sqiq = asi ** bsq;
wire signed [34:0] sqiw = asi ** bsw;
wire signed [34:0] sqqi = asq ** bsi;
wire signed [34:0] sqqq = asq ** bsq;
wire signed [34:0] sqqw = asq ** bsw;
wire signed [34:0] sqwi = asw ** bsi;
wire signed [34:0] sqwq = asw ** bsq;
wire signed [34:0] sqww = asw ** bsw;
wire signed [66:0] swii = asi ** bsi;
wire signed [66:0] swiq = asi ** bsq;
wire signed [66:0] swiw = asi ** bsw;
wire signed [66:0] swqi = asq ** bsi;
wire signed [66:0] swqq = asq ** bsq;
wire signed [66:0] swqw = asq ** bsw;
wire signed [66:0] swwi = asw ** bsi;
wire signed [66:0] swwq = asw ** bsq;
wire signed [66:0] swww = asw ** bsw;
// verilator lint_on WIDTH
task checkpow(input [66:0] ures, input signed [66:0] sres);
`ifdef TEST_VERBOSE
$write("- lastcyc%0d: %0x**%0x = %0x (exp %0x)\n", last_cyc, a, b, uwww, ures);
`endif
// verilator lint_off WIDTH
`checkh(uiii, ures[15:0]);
`checkh(uiiq, ures[15:0]);
`checkh(uiiw, ures[15:0]);
`checkh(uiqi, ures[15:0]);
`checkh(uiqq, ures[15:0]);
`checkh(uiqw, ures[15:0]);
`checkh(uiwi, ures[15:0]);
`checkh(uiwq, ures[15:0]);
`checkh(uiww, ures[15:0]);
`checkh(uqii, ures[15:0]);
`checkh(uqiq, ures[15:0]);
`checkh(uqiw, ures[15:0]);
`checkh(uqqi, ures[34:0]);
`checkh(uqqq, ures[34:0]);
`checkh(uqqw, ures[34:0]);
`checkh(uqwi, ures[34:0]);
`checkh(uqwq, ures[34:0]);
`checkh(uqww, ures[34:0]);
`checkh(uwii, ures[15:0]);
`checkh(uwiq, ures[15:0]);
`checkh(uwiw, ures[15:0]);
`checkh(uwqi, ures[34:0]);
`checkh(uwqq, ures[34:0]);
`checkh(uwqw, ures[34:0]);
`checkh(uwwi, ures[66:0]);
`checkh(uwwq, ures[66:0]);
`checkh(uwww, ures[66:0]);
`ifdef TEST_VERBOSE
$write("- lastcyc%0d: %0d**%0d = signed %0d (exp %0d)\n", last_cyc, asw, bsw, swww, sres);
`endif
// verilator lint_off WIDTH
`checkh(siii, sres[15:0]);
`checkh(siiq, sres[15:0]);
`checkh(siiw, sres[15:0]);
`checkh(siqi, sres[15:0]);
`checkh(siqq, sres[15:0]);
`checkh(siqw, sres[15:0]);
`checkh(siwi, sres[15:0]);
`checkh(siwq, sres[15:0]);
`checkh(siww, sres[15:0]);
`checkh(sqii, sres[34:0]);
`checkh(sqiq, sres[34:0]);
`checkh(sqiw, sres[34:0]);
`checkh(sqqi, sres[34:0]);
`checkh(sqqq, sres[34:0]);
`checkh(sqqw, sres[34:0]);
`checkh(sqwi, sres[34:0]);
`checkh(sqwq, sres[34:0]);
`checkh(sqww, sres[34:0]);
`checkh(swii, sres[66:0]);
`checkh(swiq, sres[66:0]);
`checkh(swiw, sres[66:0]);
`checkh(swqi, sres[66:0]);
`checkh(swqq, sres[66:0]);
`checkh(swqw, sres[66:0]);
`checkh(swwi, sres[66:0]);
`checkh(swwq, sres[66:0]);
`checkh(swww, sres[66:0]);
// verilator lint_on WIDTH
endtask
`define goldoneu(vu) \
$write("gold: u %0x**%0x: %s = %0x\n", auw, buw, `STRINGIFY(vu), vu);
`define goldones(vs) \
$write("gold: s %0d**%0d: %s = %0d\n", asw, bsw, `STRINGIFY(vs), vs);
task golddump();
// verilator lint_off WIDTH
`goldoneu(uiii);
`goldoneu(uiiq);
`goldoneu(uiiw);
`goldoneu(uiqi);
`goldoneu(uiqq);
`goldoneu(uiqw);
`goldoneu(uiwi);
`goldoneu(uiwq);
`goldoneu(uiww);
`goldoneu(uqii);
`goldoneu(uqiq);
`goldoneu(uqiw);
`goldoneu(uqqi);
`goldoneu(uqqq);
`goldoneu(uqqw);
`goldoneu(uqwi);
`goldoneu(uqwq);
`goldoneu(uqww);
`goldoneu(uwii);
`goldoneu(uwiq);
`goldoneu(uwiw);
`goldoneu(uwqi);
`goldoneu(uwqq);
`goldoneu(uwqw);
`goldoneu(uwwi);
`goldoneu(uwwq);
`goldoneu(uwww);
`goldones(siii);
`goldones(siiq);
`goldones(siiw);
`goldones(siqi);
`goldones(siqq);
`goldones(siqw);
`goldones(siwi);
`goldones(siwq);
`goldones(siww);
`goldones(sqii);
`goldones(sqiq);
`goldones(sqiw);
`goldones(sqqi);
`goldones(sqqq);
`goldones(sqqw);
`goldones(sqwi);
`goldones(sqwq);
`goldones(sqww);
`goldones(swii);
`goldones(swiq);
`goldones(swiw);
`goldones(swqi);
`goldones(swqq);
`goldones(swqw);
`goldones(swwi);
`goldones(swwq);
`goldones(swww);
// verilator lint_on WIDTH
endtask
integer cyc; initial cyc=1;
integer last_cyc;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
last_cyc <= cyc;
`ifdef TEST_VERBOSE
$write("%0x %x %x\n", cyc, p, shifted);
$write("- cyc%0d: %0x**%0x = sh %0x\n", cyc, a, b, shifted);
`endif
// Constant versions
`checkh(61'h1 ** 21'h31, 61'h1);
`checkh(61'h2 ** 21'h10, 61'h10000);
`checkh(61'd10 ** 21'h3, 61'h3e8);
`checkh(61'h3 ** 21'h7, 61'h88b);
`checkh(67'h1 ** 21'h31, 67'h1);
`checkh(67'h2 ** 21'h10, 67'h10000);
`checkh(67'd10 ** 21'h3, 67'h3e8);
`checkh(67'h3 ** 21'h7, 67'h88b);
`checkh(67'h0 ** 21'h0, 67'h1);
`checkh(67'sh0 ** 21'sh0, 67'sh1);
`checkh(67'h10 ** 21'h0, 67'h1);
`ifndef VCS
`checkh(61'h7ab3811219 ** 21'ha6e30, 61'h01ea58c703687e81);
`endif
if (cyc==1) begin
a <= 61'h0;
b <= 21'h0;
end
if (cyc==2) begin
a <= 61'h0;
b <= 21'h3;
end
if (cyc==3) begin
a <= 61'h1;
b <= 21'h31;
end
if (cyc==4) begin
a <= 61'h2;
b <= 21'h10;
end
if (cyc==5) begin
a <= 61'd10;
b <= 21'd3;
end
if (cyc==6) begin
a <= 61'd3;
b <= 21'd7;
end
if (cyc==7) begin
a <= 61'h7ab3811219;
b <= 21'ha6e30;
end
if (cyc==9) begin
if (cyc==0) begin end
else if (cyc==1) begin a <= 67'h0; b <= 67'h0; end
else if (cyc==2) begin a <= 67'h0; b <= 67'h3; end
else if (cyc==3) begin a <= 67'h1; b <= 67'h31; end
else if (cyc==4) begin a <= 67'h2; b <= 67'h10; end
else if (cyc==5) begin a <= 67'd10; b <= 67'd3; end
else if (cyc==6) begin a <= 67'd3; b <= 67'd7; end
else if (cyc==7) begin a <= 67'h7ab3811219; b <= 67'ha6e30; end
else if (cyc==10) begin a <= 67'h0; b <= 67'h0; end
else if (cyc==11) begin a <= 67'h0; b <= 67'h1; end
else if (cyc==12) begin a <= 67'h0; b <= -67'h1; end
else if (cyc==13) begin a <= 67'h0; b <= 67'h2; end
else if (cyc==14) begin a <= 67'h0; b <= 67'h3; end
else if (cyc==20) begin a <= 67'h1; b <= 67'h0; end
else if (cyc==21) begin a <= 67'h1; b <= 67'h1; end
else if (cyc==22) begin a <= 67'h1; b <= -67'h1; end
else if (cyc==23) begin a <= 67'h1; b <= 67'h2; end
else if (cyc==24) begin a <= 67'h1; b <= 67'h3; end
else if (cyc==30) begin a <= -67'h1; b <= 67'h0; end
else if (cyc==31) begin a <= -67'h1; b <= 67'h1; end
else if (cyc==32) begin a <= -67'h1; b <= -67'h1; end
else if (cyc==33) begin a <= -67'h1; b <= 67'h2; end
else if (cyc==34) begin a <= -67'h1; b <= 67'h3; end
else if (cyc==40) begin a <= 67'h2; b <= 67'h0; end
else if (cyc==41) begin a <= 67'h2; b <= 67'h1; end
else if (cyc==42) begin a <= 67'h2; b <= -67'h1; end
else if (cyc==43) begin a <= 67'h2; b <= 67'h2; end
else if (cyc==44) begin a <= 67'h2; b <= 67'h3; end
else if (cyc==50) begin a <= 67'h3; b <= 67'h0; end
else if (cyc==51) begin a <= 67'h3; b <= 67'h1; end
else if (cyc==52) begin a <= 67'h3; b <= -67'h1; end
else if (cyc==53) begin a <= 67'h3; b <= 67'h2; end
else if (cyc==54) begin a <= 67'h3; b <= 67'h3; end
else if (cyc==60) begin a <= -67'h2; b <= 67'h0; end
else if (cyc==61) begin a <= -67'h2; b <= 67'h1; end
else if (cyc==62) begin a <= -67'h2; b <= -67'h1; end
else if (cyc==63) begin a <= -67'h2; b <= 67'h2; end
else if (cyc==64) begin a <= -67'h2; b <= 67'h3; end
else if (cyc==99) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
case (cyc)
32'd00: ;
32'd01: ;
32'd02: ; // 0^x is indeterminate
32'd03: ; // 0^x is indeterminate
32'd04: `checkh(p, 61'h1);
32'd05: `checkh(p, 61'h10000);
32'd06: `checkh(p, 61'h3e8);
32'd07: `checkh(p, 61'h88b);
32'd08: `checkh(p, 61'h01ea58c703687e81);
32'd09: `checkh(p, 61'h01ea58c703687e81);
default: $stop;
// IEEE:
// op1 < -1 op1 == -1 op1 == 0 op1 == 1 op1 > 1
// op2 is positive op1 ** op2 op2 is odd -> -1, even -> 1 0 1 op1 ** op2
// op2 is zero 1 1 1 1 1
// op2 is negative 0 op2 is odd -> -1, even -> 1 'x 1 0
case (last_cyc)
32'd10: checkpow(67'h1, 67'h1); // 0 ** 0 -> 1
32'd11: checkpow(67'h0, 67'h0); // 0 ** 1 -> 1
32'd12: ; // 0 ** -1 -> x
32'd13: checkpow(67'h0, 67'h0); // 0 ** 2 -> 0
32'd14: checkpow(67'h0, 67'h0); // 0 ** 3 -> 0
32'd20: checkpow(67'h1, 67'h1); // 1 ** 0 -> 1
32'd21: checkpow(67'h1, 67'h1); // 1 ** 1 -> 1
`ifndef IVERILOG
32'd22: checkpow(67'h1, 67'h1); // 1 ** -1 -> 1
`endif
32'd23: checkpow(67'h1, 67'h1); // 1 ** 2 -> 1
32'd24: checkpow(67'h1, 67'h1); // 1 ** 3 -> 1
32'd30: checkpow(67'h1, 67'h1); // -1 ** 0 -> 1
32'd31: checkpow(-67'h1, -67'h1); // -1 ** 1 -> -1 if odd else 1
32'd32: golddump(); // -1 ** -1 SEE GOLDEN
32'd33: golddump(); // -1 ** 2 SEE GOLDEN
32'd34: golddump(); // -1 ** 3 SEE GOLDEN
32'd40: checkpow(67'h1, 67'h1); // 2 ** 0 -> 1
32'd41: checkpow(67'h2, 67'h2); // 2 ** 1
32'd42: checkpow(67'h0, 67'h0); // 2 ** -1 -> 0
32'd43: checkpow(67'h4, 67'h4); // 2 ** 2
32'd44: checkpow(67'h8, 67'h8); // 2 ** 3
32'd50: checkpow(67'h1, 67'h1); // 3 ** 0 -> 0
32'd51: checkpow(67'h3, 67'h3); // 3 ** 1
32'd52: golddump(); // 3 ** -1 -> 0 (if negative gives 0)
32'd53: checkpow(67'h9, 67'h9); // 3 ** 2
32'd54: checkpow(67'h1b, 67'h1b); // 3 ** 3
32'd60: checkpow(67'h1, 67'h1); // -2 ** 0 -> 1
32'd61: golddump(); // -2 ** 1 SEE GOLDEN
32'd62: golddump(); // -2 ** -1 SEE GOLDEN
32'd63: golddump(); // -2 ** 2 SEE GOLDEN
32'd64: golddump(); // -2 ** 3 SEE GOLDEN
default: ;
endcase
case (cyc)
32'd00: ;
32'd01: ;
32'd02: `checkh(shifted, 61'h0000000000000001);
32'd03: `checkh(shifted, 61'h0000000000000008);
32'd04: `checkh(shifted, 61'h0002000000000000);
32'd05: `checkh(shifted, 61'h0000000000010000);
32'd06: `checkh(shifted, 61'h0000000000000008);
32'd07: `checkh(shifted, 61'h0000000000000080);
32'd08: `checkh(shifted, 61'h0000000000000000);
32'd09: `checkh(shifted, 61'h0000000000000000);
default: $stop;
32'd02: `checkh(shifted, 67'h0000000000000001);
32'd03: `checkh(shifted, 67'h0000000000000008);
32'd04: `checkh(shifted, 67'h0002000000000000);
32'd05: `checkh(shifted, 67'h0000000000010000);
32'd06: `checkh(shifted, 67'h0000000000000008);
32'd07: `checkh(shifted, 67'h0000000000000080);
32'd08: `checkh(shifted, 67'h0000000000000000);
32'd09: `checkh(shifted, 67'h0000000000000000);
default: ;
endcase
end
endmodule

View File

@ -45,7 +45,7 @@ module t (/*AUTOARG*/);
`checkh((-8'sh1 ** 8'sh2), 8'h1 ); // -1^odd=-1, -1^even=1
`checkh((-8'sh1 ** 8'sh3), 8'hff ); // -1^odd=-1, -1^even=1
`checkh(( 8'h0 ** 8'sh3), 8'h0 ); // 0
`checkh(( 8'h1 ** 8'sh3), 8'h1 ); // 1
`checkh(( 8'h1 ** 8'sh3), 8'h1 ); // 1
`checkh(( 8'h3 ** 8'sh3), 8'h1b ); // a**b (27)
`checkh(( 8'sh3 ** 8'sh3), 8'h1b ); // a**b (27)
`checkh(( 8'h6 ** 8'sh3), 8'hd8 ); // a**b (216)

View File

@ -18,7 +18,7 @@ module t (/*AUTOARG*/
// -- Verilator 621c515 creates code that uses the undeclared function VL_POW_WWI()
// verilator lint_off WIDTH
output [3:0] i65 = 65'd3 ** a; // WWI
output [3:0] i65 = 65'd3 ** a; // IWI
output [3:0] j65 = a ** 65'd3; // IIW
output [3:0] i33 = 33'd3 ** a; // QQI
output [3:0] j33 = a ** 33'd3; // IIQ