github/verilator
1
0
Fork 1
mirror of https://github.com/verilator/verilator.git synced 2025-01-06 06:37:45 +00:00
Code Issues Packages Projects Releases Wiki Activity

Commentary, bug1288.

Browse Source
This commit is contained in:
Wilson Snyder 2018-03-09 00:04:00 -05:00
parent 22ff760f0b
commit 9ae54786e4
1 changed files with 4 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
bin/verilator
View File

@ -3055,13 +3055,14 @@ Simply use a different register for the flop:
always @* foo[0] = foo_flopped[0]; always @* foo[0] = foo_flopped[0];
always @* foo[1] = ... always @* foo[1] = ...
It is also possible to disable this error when one of the assignments is
inside a public task.
This is not illegal in SystemVerilog, but a violation of good coding This is not illegal in SystemVerilog, but a violation of good coding
practice. Verilator reports this as an error, because ignoring this warning practice. Verilator reports this as an error, because ignoring this warning
may make Verilator simulations differ from other simulators. may make Verilator simulations differ from other simulators.
It is generally safe to disable this error when one of the assignments is
inside a public task, or when the blocked and non-blocking assignments have
non-overlapping bits and structure members.
=item BLKSEQ =item BLKSEQ
This indicates that a blocking assignment (=) is used in a sequential This indicates that a blocking assignment (=) is used in a sequential