Fix --output-split-cfunc to count internal functions.

Changes

@@ -7,6 +7,9 @@ indicates the contributor was also the author of the fix; Thanks!
 
 ***   Support named function and task arguments. [Chris Randall]
 
+****  Fix --output-split-cfunc to count internal functions. [Chris Randall]
+
+
 
 * Verilator 3.851 2013-08-15
 

bin/verilator

@@ -300,7 +300,8 @@ descriptions in the next sections for more information.
      -O<optimization-letter>    Selectable optimizations
      -o <executable>            Name of final executable
     --output-split <bytes>      Split .cpp files into pieces
-    --output-split-cfuncs <statements>   Split .ccp functions
+    --output-split-cfuncs <statements>   Split .cpp functions
+    --output-split-ctrace <statements>   Split tracing functions
     --pins-bv <bits>            Specify types for top level ports
     --pins-sc-uint              Specify types for top level ports
     --pins-sc-biguint           Specify types for top level ports
@@ -810,6 +811,11 @@ worse with decreasing split values.  Note that this option is stronger than
 --output-split in the sense that --output-split will not split inside a
 function.
 
+=item --output-split-ctrace I<statements>
+
+Enables splitting trace functions in the output .cpp/.sp files into
+multiple functions.  Defaults to same setting as --output-split-cfuncs.
+
 =item --pins64
 
 Backward compatible alias for "--pins-bv 65".  Note that's a 65, not a 64.

src/V3EmitC.cpp

@@ -58,8 +58,9 @@ public:
     int	splitFilenum() const { return m_splitFilenum; }
     int	splitFilenumInc() { m_splitSize = 0; return ++m_splitFilenum; }
     int splitSize() const { return m_splitSize; }
-    void splitSizeInc(AstNode* nodep) { m_splitSize += EmitCBaseCounterVisitor(nodep).count(); }
-    bool splitNeeded() { return (splitSize() && v3Global.opt.outputSplit() > 1
+    void splitSizeInc(int count) { m_splitSize += count; }
+    void splitSizeInc(AstNode* nodep) { splitSizeInc(EmitCBaseCounterVisitor(nodep).count()); }
+    bool splitNeeded() { return (splitSize() && v3Global.opt.outputSplit()
 				 && v3Global.opt.outputSplit() < splitSize()); }
 
     // METHODS
@@ -1418,9 +1419,11 @@ void EmitCImp::emitConfigureImp(AstNodeModule* modp) {
 		puts("// Coverage Declarations\n");
 	    }
 	    nodep->accept(*this);
+	    splitSizeInc(nodep);
 	}
     }
     puts("}\n");
+    splitSizeInc(10);
 }
 
 void EmitCImp::emitCoverageImp(AstNodeModule* modp) {
@@ -1444,6 +1447,7 @@ void EmitCImp::emitCoverageImp(AstNodeModule* modp) {
 	puts(	"  \"page\",pagep,");
 	puts(	"  \"comment\",commentp);\n");
 	puts("}\n");
+	splitSizeInc(10);
     }
 }
 
@@ -1453,6 +1457,7 @@ void EmitCImp::emitDestructorImp(AstNodeModule* modp) {
     emitTextSection(AstType::atSCDTOR);
     if (modp->isTop()) puts("delete __VlSymsp; __VlSymsp=NULL;\n");
     puts("}\n");
+    splitSizeInc(10);
 }
 
 void EmitCImp::emitSavableImp(AstNodeModule* modp) {
@@ -1631,6 +1636,7 @@ void EmitCImp::emitWrapEval(AstNodeModule* modp) {
     puts("}\n");
 #endif
     puts("}\n");
+    splitSizeInc(10);
 
     //
     puts("\nvoid "+modClassName(modp)+"::_eval_initial_loop("+EmitCBaseVisitor::symClassVar()+") {\n");
@@ -1651,6 +1657,7 @@ void EmitCImp::emitWrapEval(AstNodeModule* modp) {
     puts(    "}\n");
 #endif
     puts("}\n");
+    splitSizeInc(10);
 }
 
 //----------------------------------------------------------------------
@@ -2111,6 +2118,7 @@ class EmitCTrace : EmitCStmts {
 	       +", &"+topClassName()+"::traceFull"
 	       +", &"+topClassName()+"::traceChg, this);\n");
 	puts("}\n");
+	splitSizeInc(10);
 
 	puts("void "+topClassName()+"::traceInit("
 	     +v3Global.opt.traceClassBase()+"* vcdp, void* userthis, uint32_t code) {\n");
@@ -2123,6 +2131,7 @@ class EmitCTrace : EmitCStmts {
 	puts("t->traceInitThis (vlSymsp, vcdp, code);\n");
 	puts("vcdp->scopeEscape('.');\n");  // Restore so SystemPerl traced files won't break
 	puts("}\n");
+	splitSizeInc(10);
 
 	puts("void "+topClassName()+"::traceFull("
 	     +v3Global.opt.traceClassBase()+"* vcdp, void* userthis, uint32_t code) {\n");
@@ -2131,6 +2140,7 @@ class EmitCTrace : EmitCStmts {
 	puts(EmitCBaseVisitor::symClassVar()+" = t->__VlSymsp; // Setup global symbol table\n");
 	puts("t->traceFullThis (vlSymsp, vcdp, code);\n");
 	puts("}\n");
+	splitSizeInc(10);
 
 	puts("\n//======================\n\n");
     }
@@ -2147,6 +2157,7 @@ class EmitCTrace : EmitCStmts {
 	puts("t->traceChgThis (vlSymsp, vcdp, code);\n");
 	puts("}\n");
 	puts("}\n");
+	splitSizeInc(10);
 
 	puts("\n//======================\n\n");
     }

test_regress/driver.pl

@@ -320,6 +320,7 @@ sub new {
 	make_pli => 0,		# need to compile pli
 	sim_time => 1100,
 	benchmark => $opt_benchmark,
+	verbose => $opt_verbose,
 	run_env => '',
 	# All compilers
 	v_flags => [split(/\s+/,(" -f input.vc "

test_regress/t/t_flag_csplit.pl

@@ -0,0 +1,55 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+$Self->{vlt} or $Self->skip("Verilator only test");
+
+compile (
+    v_flags2 => ["--trace --output-split 1 --output-split-cfuncs 1"],
+    );
+
+execute (
+    check_finished=>1,
+    );
+
+my $got1;
+foreach my $file (glob("$Self->{obj_dir}/*.cpp")) {
+    $got1 = 1 if $file =~ /__1/;
+    check($file);
+}
+$got1 or $Self->error("No __1 split file found");
+
+ok(1);
+1;
+
+
+sub check {
+    my $filename = shift;
+    my $size = -s $filename;
+    printf "  File %6d  %s\n", $size, $filename if $Self->{verbose};
+    my $fh = IO::File->new("<$filename") or $Self->error("$! $filenme");
+    my @funcs;
+    while (defined (my $line = $fh->getline)) {
+	if ($line =~ /^(void|IData)\s+(.*::.*)/) {
+	    my $func = $2;
+	    $func =~ s/\(.*$//;
+	    print "\tFunc $func\n" if $Self->{verbose};
+	    if ($func !~ /::_eval_initial_loop$/
+		&& $func !~ /::__Vconfigure$/
+		&& $func !~ /::trace$/
+		&& $func !~ /::traceInit$/
+		&& $func !~ /::traceFull$/
+		) {
+		push @funcs, $func;
+	    }
+	}
+    }
+    if ($#funcs > 0) {
+	$Self->error("Split had multiple functions in $filename\n\t".join("\n\t",@funcs));
+    }
+}

test_regress/t/t_flag_csplit.v

@@ -0,0 +1,48 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2005 by Wilson Snyder.
+
+module t (/*AUTOARG*/
+   // Inputs
+   clk
+   );
+   input clk;
+
+   integer 	cyc=0;
+
+   parameter CNT = 10;
+
+   wire [31:0] 	w [CNT:0];
+
+   generate
+      for (genvar g=0; g<CNT; g++)
+	sub sub (.clk(clk), .i(w[g]), .z(w[g+1]));
+   endgenerate
+
+   // Test loop
+   always @ (posedge clk) begin
+      cyc <= cyc + 1;
+      if (cyc==0) begin
+	 // Setup
+	 w[0] = 32'h1234;
+      end
+      else if (cyc<90) begin
+      end
+      else if (cyc==99) begin
+`define EXPECTED_SUM 32'h123e
+`ifdef TEST_VERBOSE
+	 $write("[%0t] cyc==%0d  sum=%x\n",$time, cyc, w[CNT]);
+`endif
+	 if (w[CNT] !== `EXPECTED_SUM) $stop;
+	 $write("*-* All Finished *-*\n");
+	 $finish;
+      end
+   end
+
+endmodule
+
+module sub (input clk, input [31:0] i, output [31:0] z);
+   always @(posedge clk)
+     z <= i+1+$c("0");  // $c so doesn't optimize away
+endmodule