From 9a133ced2d9b5411331893c4eaa2f8bc25ec55f1 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Sat, 31 Oct 2009 15:12:28 -0400
Subject: [PATCH] Support 'bit' keyword

---
 bin/verilator |  2 +-
 src/verilog.l |  2 +-
 src/verilog.y | 24 ++++++++++++++++++------
 3 files changed, 20 insertions(+), 8 deletions(-)

diff --git a/bin/verilator b/bin/verilator
index 02e51bf8b..dbea87bae 100755
--- a/bin/verilator
+++ b/bin/verilator
@@ -1179,7 +1179,7 @@ including function call-like preprocessor defines.
 
 Verilator supports ==? and !=? operators, $bits, $countones, $error,
 $fatal, $info, $isunknown, $onehot, $onehot0, $warning, always_comb,
-always_ff, always_latch, do-while, final, logic, priority case/if, and
+always_ff, always_latch, bit, do-while, final, logic, priority case/if, and
 unique case/if.
 
 It also supports .name and .* interconnection.
diff --git a/src/verilog.l b/src/verilog.l
index 9acf119fe..3a738f7f1 100644
--- a/src/verilog.l
+++ b/src/verilog.l
@@ -360,6 +360,7 @@ escid	\\[^ \t\f\r\n]+
   "always_comb"		{ FL; return yALWAYS; }
   "always_ff"		{ FL; return yALWAYS; }
   "always_latch"	{ FL; return yALWAYS; }
+  "bit"			{ FL; return yBIT; }
   "clocking"		{ FL; return yCLOCKING; }
   "do"			{ FL; return yDO; }
   "endclocking"		{ FL; return yENDCLOCKING; }
@@ -380,7 +381,6 @@ escid	\\[^ \t\f\r\n]+
   "bind"		{ yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); }
   "bins"		{ yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); }
   "binsof"		{ yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); }
-  "bit"			{ yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); }
   "break"		{ yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); }
   "byte"		{ yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); }
   "chandle"		{ yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); }
diff --git a/src/verilog.y b/src/verilog.y
index 0347f46b4..4d6a49800 100644
--- a/src/verilog.y
+++ b/src/verilog.y
@@ -206,6 +206,7 @@ class AstSenTree;
 %token<fl>		yASSIGN		"assign"
 %token<fl>		yAUTOMATIC	"automatic"
 %token<fl>		yBEGIN		"begin"
+%token<fl>		yBIT		"bit"
 %token<fl>		yBUF		"buf"
 %token<fl>		yBUFIF0		"bufif0"
 %token<fl>		yBUFIF1		"bufif1"
@@ -792,6 +793,21 @@ tf_port_declaration<nodep>:	// ==IEEE: tf_port_declaration
 	//UNSUP	port_directionReset yVAR implicit_type { VARTYPE($3); }  list_of_tf_variable_identifiers ';'	{ $$ = $5; }
 	;
 
+integer_atom_type<rangep>:	// ==IEEE: integer_atom_type
+	//UNSUP	yBYTE					{ UNSUP }
+	//UNSUP	ySHORTINT				{ UNSUP }
+	//UNSUP	yINT					{ UNSUP }
+	//UNSUP	yLONGINT				{ UNSUP }
+		yINTEGER				{ VARDECL(INTEGER); $$ = new AstRange($1,31,0); $$->isSigned(true); }
+	//UNSUP	yTIME					{ UNSUP }
+	;
+
+integer_vector_type:		// ==IEEE: integer_atom_type
+		yBIT					{ VARDECL(REG); }
+	|	yLOGIC					{ VARDECL(REG); }
+	|	yREG					{ VARDECL(REG); }
+	;
+
 signingE:			// IEEE: signing - plus empty
 		/*empty*/ 				{ }
 	|	signing					{ }
@@ -818,12 +834,8 @@ data_type<rangep>:		// ==IEEE: data_type
 	;
 
 data_typeNoRef<rangep>:		// ==IEEE: data_type, excluding class_type etc references
-		yINTEGER				{ VARDECL(INTEGER); $$ = new AstRange($1,31,0); $$->isSigned(true); }
-	|	yREG signingE rangeListE		{ VARDECL(REG); $$ = $3; }
-	|	yLOGIC signingE rangeListE		{ VARDECL(REG); $$ = $3; }
-	//UNSUP: above instead of integer_type
-	//
-	//UNSUP	integer_type signingE regArRangeE	{ UNSUP }
+		integer_vector_type signingE rangeListE	{ $$ = $3; }
+	|	integer_atom_type signingE		{ $$ = $1; }
 	//UNSUP	non_integer_type			{ UNSUP }
 	//UNSUP	ySTRUCT        packedSigningE '{' struct_union_memberList '}' packed_dimensionE	{ UNSUP }
 	//UNSUP	yUNION taggedE packedSigningE '{' struct_union_memberList '}' packed_dimensionE	{ UNSUP }