Tests: Remove unstable new test

test_regress/t/t_let_side.pl

@@ -1,21 +0,0 @@
-#!/usr/bin/env perl
-if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
-# DESCRIPTION: Verilator: Verilog Test driver/expect definition
-#
-# Copyright 2023 by Wilson Snyder. This program is free software; you
-# can redistribute it and/or modify it under the terms of either the GNU
-# Lesser General Public License Version 3 or the Perl Artistic License
-# Version 2.0.
-# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
-
-scenarios(vlt => 1);
-
-compile(
-    );
-
-execute(
-    check_finished => 1,
-    );
-
-ok(1);
-1;

test_regress/t/t_let_side.v

@@ -1,29 +0,0 @@
-// DESCRIPTION: Verilator: Verilog Test module
-//
-// This file ONLY is placed under the Creative Commons Public Domain, for
-// any use, without warranty, 2023 by Wilson Snyder.
-// SPDX-License-Identifier: CC0-1.0
-
-module t(/*AUTOARG*/);
-
-   let F(a) = {a, a, a};
-
-   function byte g();
-      static byte r = 0;
-      return ++r;
-   endfunction
-
-   bit [23:0]     res;
-
-   initial begin
-      res = F(g());
-      $display("%h", res);
-      // Commercial1     010101 -- seems wrong by my reading of IEEE but anyhow
-      // Commercial2/Vlt 010203
-      // Commercial3/4   030201
-      if (res != 24'h010101 && res != 24'h010203 && res != 24'h030201) $stop;
-      $write("*-* All Finished *-*\n");
-      $finish;
-   end
-
-endmodule