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https://github.com/verilator/verilator.git
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CDC: Fix columns mis-aligning when large filename paths
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Wilson Snyder
parent
b6447a9032
commit
97adede70b
@ -110,15 +110,19 @@ public:
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class CdcLogicVertex : public CdcEitherVertex {
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bool m_safe;
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bool m_isFlop;
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public:
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CdcLogicVertex(V3Graph* graphp, AstScope* scopep, AstNode* nodep, AstSenTree* sensenodep)
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: CdcEitherVertex(graphp,scopep,nodep), m_safe(true) { srcDomainp(sensenodep); dstDomainp(sensenodep); }
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: CdcEitherVertex(graphp,scopep,nodep), m_safe(true), m_isFlop(false)
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{ srcDomainp(sensenodep); dstDomainp(sensenodep); }
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virtual ~CdcLogicVertex() {}
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// Accessors
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virtual string name() const { return (cvtToStr((void*)nodep())+"@"+scopep()->prettyName()); }
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virtual string dotColor() const { return safe() ? "black" : "yellow"; }
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bool safe() const { return m_safe; }
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void clearSafe(AstNode* nodep) { m_safe = false; nodep->user3(true); }
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bool isFlop() const { return m_isFlop; }
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void isFlop(bool flag) { m_isFlop = flag; }
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};
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//######################################################################
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@ -158,6 +162,42 @@ public:
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virtual ~CdcDumpVisitor() {}
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};
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//######################################################################
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class CdcWidthVisitor : public CdcBaseVisitor {
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private:
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int m_maxLineno;
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int m_maxFilenameLen;
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virtual void visit(AstNode* nodep, AstNUser*) {
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nodep->iterateChildren(*this);
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// Keeping line+filename lengths separate is much faster than calling ascii().length()
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if (nodep->fileline()->lineno() >= m_maxLineno) {
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m_maxLineno = nodep->fileline()->lineno()+1;
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}
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if (nodep->fileline()->filename().length() >= m_maxFilenameLen) {
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m_maxFilenameLen = nodep->fileline()->filename().length()+1;
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}
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}
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public:
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// CONSTUCTORS
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CdcWidthVisitor(AstNode* nodep) {
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m_maxLineno = 0;
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m_maxFilenameLen = 0;
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nodep->accept(*this);
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}
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virtual ~CdcWidthVisitor() {}
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// ACCESSORS
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int maxWidth() {
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int width=1;
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width += m_maxFilenameLen;
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width += 1; // The :
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width += cvtToStr(m_maxLineno).length();
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width += 1; // Final :
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return width;
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}
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};
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//######################################################################
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// Cdc class functions
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@ -182,6 +222,7 @@ private:
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string m_ofFilename; // Output filename
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ofstream* m_ofp; // Output file
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uint32_t m_userGeneration; // Generation count to avoid slow userClearVertices
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int m_filelineWidth; // Characters in longest fileline
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// METHODS
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void iterateNewStmt(AstNode* nodep) {
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@ -189,6 +230,7 @@ private:
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UINFO(4," STMT "<<nodep<<endl);
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m_logicVertexp = new CdcLogicVertex(&m_graph, m_scopep, nodep, m_domainp);
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if (m_domainp && m_domainp->hasClocked()) { // To/from a flop
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m_logicVertexp->isFlop(true);
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m_logicVertexp->srcDomainp(m_domainp);
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m_logicVertexp->srcDomainSet(true);
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m_logicVertexp->dstDomainp(m_domainp);
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@ -266,6 +308,14 @@ private:
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analyzeReset();
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}
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int filelineWidth() {
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if (!m_filelineWidth) {
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CdcWidthVisitor visitor (v3Global.rootp());
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m_filelineWidth = visitor.maxWidth();
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}
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return m_filelineWidth;
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}
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//----------------------------------------
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// RESET REPORT
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@ -344,9 +394,15 @@ private:
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*m_ofp<<"\n";
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*m_ofp<<"\n";
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CdcEitherVertex* targetp = vertexp; // One example destination flop (of possibly many)
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if (V3GraphEdge* edgep = vertexp->outBeginp()) {
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for (V3GraphEdge* edgep = vertexp->outBeginp(); edgep; edgep = edgep->outNextp()) {
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CdcEitherVertex* eToVertexp = (CdcEitherVertex*)edgep->top();
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targetp = eToVertexp;
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if (!eToVertexp) targetp = eToVertexp;
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if (CdcLogicVertex* vvertexp = dynamic_cast<CdcLogicVertex*>(eToVertexp)) {
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if (vvertexp->isFlop()) {
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targetp = eToVertexp;
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break;
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}
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} // else it might be random logic that's not relevant
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}
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warnAndFile(markp->nodep(),V3ErrorCode::CDCRSTLOGIC,"Logic in path that feeds async reset, via signal: "+nodep->prettyName());
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dumpAsyncRecurse(targetp, "", " ",0);
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@ -372,19 +428,20 @@ private:
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// Dump single variable/logic block
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// See also OrderGraph::loopsVertexCb(V3GraphVertex* vertexp)
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AstNode* nodep = vertexp->nodep();
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string front = pad(40,nodep->fileline()->ascii()+":")+" "+prefix+" +- ";
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string front = pad(filelineWidth(),nodep->fileline()->ascii()+":")+" "+prefix+" +- ";
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if (nodep->castVarScope()) {
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*m_ofp<<front<<"Variable: "<<nodep->prettyName()<<endl;
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}
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else {
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V3EmitV::verilogPrefixedTree(nodep, *m_ofp, prefix+" +- ", vertexp->srcDomainp(), true);
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V3EmitV::verilogPrefixedTree(nodep, *m_ofp, prefix+" +- ", filelineWidth(),
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vertexp->srcDomainp(), true);
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if (debug()) {
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CdcDumpVisitor visitor (nodep, m_ofp, front+"DBG: ");
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}
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}
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nextsep = " | ";
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if (level) *m_ofp<<V3OutFile::indentSpaces(40)<<" "<<prefix<<nextsep<<"\n";
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if (level) *m_ofp<<V3OutFile::indentSpaces(filelineWidth())<<" "<<prefix<<nextsep<<"\n";
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return true;
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}
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@ -428,7 +485,8 @@ private:
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if (vvertexp->srcDomainp()) V3EmitV::verilogForTree(vvertexp->srcDomainp(), os);
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os<<" DST=";
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if (vvertexp->dstDomainp()) V3EmitV::verilogForTree(vvertexp->dstDomainp(), os);
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os<<"\n";
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os<<setw(0);
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os<<endl;
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report.push_back(os.str());
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}
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}
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@ -627,6 +685,7 @@ public:
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m_inDly = false;
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m_senNumber = 0;
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m_userGeneration = 0;
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m_filelineWidth = 0;
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// Make report of all signal names and what clock edges they have
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string filename = v3Global.opt.makeDir()+"/"+v3Global.opt.prefix()+"__cdc.txt";
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@ -643,7 +702,7 @@ public:
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analyze();
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//edgeReport(); // Not useful at the moment
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if (0) { *m_ofp<<"\nDBG-test-dumper\n"; V3EmitV::verilogPrefixedTree(nodep, *m_ofp, "DBG ",NULL,true); *m_ofp<<endl; }
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if (0) { *m_ofp<<"\nDBG-test-dumper\n"; V3EmitV::verilogPrefixedTree(nodep, *m_ofp, "DBG ",40,NULL,true); *m_ofp<<endl; }
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}
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virtual ~CdcVisitor() {
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if (m_ofp) { delete m_ofp; m_ofp = NULL; }
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@ -543,6 +543,7 @@ class EmitVStreamVisitor : public EmitVBaseVisitor {
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class EmitVPrefixedFormatter : public V3OutFormatter {
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ostream& m_os;
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string m_prefix; // What to print at beginning of each line
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int m_flWidth; // Padding of fileline
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int m_column; // Rough location; need just zero or non-zero
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FileLine* m_prefixFl;
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// METHODS
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@ -554,7 +555,7 @@ class EmitVPrefixedFormatter : public V3OutFormatter {
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if (m_column == 0) {
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m_column = 10;
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m_os<<m_prefixFl->ascii()+":";
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m_os<<V3OutFile::indentSpaces(40-(m_prefixFl->ascii().length()+1));
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m_os<<V3OutFile::indentSpaces(m_flWidth-(m_prefixFl->ascii().length()+1));
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m_os<<" ";
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m_os<<m_prefix;
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}
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@ -566,8 +567,8 @@ public:
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void prefixFl(FileLine* fl) { m_prefixFl = fl; }
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FileLine* prefixFl() const { return m_prefixFl; }
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int column() const { return m_column; }
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EmitVPrefixedFormatter(ostream& os, const string& prefix)
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: V3OutFormatter("__STREAM", true), m_os(os), m_prefix(prefix) {
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EmitVPrefixedFormatter(ostream& os, const string& prefix, int flWidth)
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: V3OutFormatter("__STREAM", true), m_os(os), m_prefix(prefix), m_flWidth(flWidth) {
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m_column = 0;
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m_prefixFl = v3Global.rootp()->fileline(); // NETLIST's fileline instead of NULL to avoid NULL checks
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}
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@ -598,9 +599,9 @@ class EmitVPrefixedVisitor : public EmitVBaseVisitor {
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}
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public:
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EmitVPrefixedVisitor(AstNode* nodep, ostream& os, const string& prefix,
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EmitVPrefixedVisitor(AstNode* nodep, ostream& os, const string& prefix, int flWidth,
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AstSenTree* domainp, bool user3mark)
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: EmitVBaseVisitor(domainp), m_formatter(os, prefix), m_user3mark(user3mark) {
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: EmitVBaseVisitor(domainp), m_formatter(os, prefix, flWidth), m_user3mark(user3mark) {
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if (user3mark) { AstUser3InUse::check(); }
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nodep->accept(*this);
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}
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@ -633,7 +634,7 @@ void V3EmitV::verilogForTree(AstNode* nodep, ostream& os) {
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EmitVStreamVisitor(nodep, os);
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}
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void V3EmitV::verilogPrefixedTree(AstNode* nodep, ostream& os, const string& prefix,
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void V3EmitV::verilogPrefixedTree(AstNode* nodep, ostream& os, const string& prefix, int flWidth,
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AstSenTree* domainp, bool user3mark) {
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EmitVPrefixedVisitor(nodep, os, prefix, domainp, user3mark);
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EmitVPrefixedVisitor(nodep, os, prefix, flWidth, domainp, user3mark);
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}
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@ -33,7 +33,7 @@ class V3EmitV {
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public:
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static void emitv();
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static void verilogForTree(AstNode* nodep, ostream& os=cout);
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static void verilogPrefixedTree(AstNode* nodep, ostream& os, const string& prefix,
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static void verilogPrefixedTree(AstNode* nodep, ostream& os, const string& prefix, int flWidth,
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AstSenTree* domainp, bool user3percent);
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};
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