From 976af0068b808e3f22f13ef10df005c0de962fd9 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Wed, 1 Mar 2023 23:11:48 -0500
Subject: [PATCH] Support parsing min:typ:max parameters

---
 src/verilog.y                       |  4 ++--
 test_regress/t/t_param_mintypmax.pl | 21 +++++++++++++++++++++
 test_regress/t/t_param_mintypmax.v  | 17 +++++++++++++++++
 3 files changed, 40 insertions(+), 2 deletions(-)
 create mode 100755 test_regress/t/t_param_mintypmax.pl
 create mode 100644 test_regress/t/t_param_mintypmax.v

diff --git a/src/verilog.y b/src/verilog.y
index cfc1642a5..6232f9091 100644
--- a/src/verilog.y
+++ b/src/verilog.y
@@ -2940,7 +2940,7 @@ delay_control<delayp>:   //== IEEE: delay_control
         |       '#' '(' minTypMax ',' minTypMax ')'
                         { $$ = new AstDelay{$<fl>1, $3, false}; RISEFALLDLYUNSUP($3); DEL($5); }
         |       '#' '(' minTypMax ',' minTypMax ',' minTypMax ')'
-                        { $$ = new AstDelay{$<fl>1, $3, false}; RISEFALLDLYUNSUP($3); DEL($5); DEL($7); }
+                        { $$ = new AstDelay{$<fl>1, $3, false}; RISEFALLDLYUNSUP($5); DEL($3); DEL($7); }
         ;
 
 delay_value<nodeExprp>:         // ==IEEE:delay_value
@@ -4785,7 +4785,7 @@ expr<nodeExprp>:                // IEEE: part of expression/constant_expression/
         //                      // IEEE: '(' mintypmax_expression ')'
         |       ~noPar__IGNORE~'(' expr ')'             { $$ = $2; }
         |       ~noPar__IGNORE~'(' expr ':' expr ':' expr ')'
-                        { $$ = $2; BBUNSUP($1, "Unsupported: min typ max expressions"); }
+                        { $$ = $4; MINTYPMAXDLYUNSUP($4); DEL($2); DEL($6); }
         //                      // PSL rule
         |       '_' '(' expr ')'                        { $$ = $3; }    // Arbitrary Verilog inside PSL
         //
diff --git a/test_regress/t/t_param_mintypmax.pl b/test_regress/t/t_param_mintypmax.pl
new file mode 100755
index 000000000..b46d46042
--- /dev/null
+++ b/test_regress/t/t_param_mintypmax.pl
@@ -0,0 +1,21 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(simulator => 1);
+
+compile(
+    );
+
+execute(
+    check_finished => 1,
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_param_mintypmax.v b/test_regress/t/t_param_mintypmax.v
new file mode 100644
index 000000000..dd9acdb5a
--- /dev/null
+++ b/test_regress/t/t_param_mintypmax.v
@@ -0,0 +1,17 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2023 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+module t (/*AUTOARG*/);
+
+   parameter MTM = (1:2:3);
+
+   initial begin
+      if (MTM != 2) $stop;
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+
+endmodule