mirror of
https://github.com/verilator/verilator.git
synced 2025-01-01 04:07:34 +00:00
parent
fd0703b8c8
commit
959387b69f
@ -14,6 +14,7 @@ Ameya Vikram Singh
|
||||
Andreas Kuster
|
||||
Andrei Kostovski
|
||||
Andrew Nolte
|
||||
Anthony Donlon
|
||||
Arkadiusz Kozdra
|
||||
Aylon Chaim Porat
|
||||
Cameron Kirk
|
||||
|
@ -5863,6 +5863,7 @@ property_declarationFront<nodeFTaskp>: // IEEE: part of property_declaration
|
||||
|
||||
property_port_listE<nodep>: // IEEE: [ ( [ property_port_list ] ) ]
|
||||
/* empty */ { $$ = nullptr; }
|
||||
| '(' ')' { $$ = nullptr; }
|
||||
| '(' property_port_list ')' { $$ = $2; }
|
||||
;
|
||||
|
||||
|
@ -60,12 +60,19 @@ module t (/*AUTOARG*/
|
||||
logic out = 1;
|
||||
|
||||
property prop_a;
|
||||
@(posedge clk) disable iff (cyc <= 10) out;
|
||||
endproperty
|
||||
@(posedge clk) disable iff (cyc <= 1) out;
|
||||
endproperty : prop_a
|
||||
|
||||
property prop_b();
|
||||
@(posedge clk) disable iff (cyc <= 1) out;
|
||||
endproperty : prop_b
|
||||
|
||||
assert property(disable iff (cyc < 5) check_if_gt_5(cyc + 1));
|
||||
assert property(@(posedge clk) pass_assertion(cyc));
|
||||
assert property (prop_a) else $error($sformatf("property check failed :assert: (False)"));
|
||||
assert property (prop_a()) else $error($sformatf("property check failed :assert: (False)"));
|
||||
assert property (prop_b) else $error($sformatf("property check failed :assert: (False)"));
|
||||
assert property (prop_b()) else $error($sformatf("property check failed :assert: (False)"));
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (expected_fails == 2) begin
|
||||
|
Loading…
Reference in New Issue
Block a user