Add t_case_write test

git-svn-id: file://localhost/svn/verilator/trunk/verilator@811 77ca24e4-aefa-0310-84f0-b9a241c72d87

test_regress/t/t_case_write.pl

@@ -0,0 +1,22 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
+# $Id$
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003-2006 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# General Public License or the Perl Artistic License.
+
+$golden_out ||= "t/$Last_Self->{name}.out";
+
+compile (
+	 v_flags2 => [$Last_Self->{v3}?"--stats --O3 -x-assign 0":""],
+	 );
+
+execute (
+	 check_finished=>1,
+     );
+
+ok(files_identical("obj_dir/$Last_Self->{name}_logger.log", $golden_out));
+
+1;

test_regress/t/t_case_write.v

@@ -0,0 +1,44 @@
+// $Id$
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2006 by Wilson Snyder.
+
+`include "verilated.v"
+
+module t (/*AUTOARG*/
+   // Inputs
+   clk
+   );
+
+   input clk;
+
+   reg [63:0] crc;
+   `verilator_file_descriptor	  fd;
+
+   t_case_write_tasks tasks ();
+
+   integer cyc; initial cyc=0;
+
+   always @ (posedge clk) begin
+      $fwrite(fd, "[%03d] ", cyc);
+      tasks.big_case(fd, crc[31:0]);
+      $fwrite(fd, "\n");
+   end
+
+   always @ (posedge clk) begin
+      //$write("[%0t] cyc==%0d crc=%x\n",$time, cyc, crc);
+      cyc <= cyc + 1;
+      crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
+      if (cyc==1) begin
+	 crc <= 64'h00000000_00000097;
+	 $write("Open obj_dir/t_case_write_logger.log\n");
+	 fd = $fopen("obj_dir/t_case_write_logger.log", "w");
+      end
+      if (cyc==90) begin
+	 $write("*-* All Finished *-*\n");
+	 $finish;
+      end
+   end
+
+endmodule