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Add Verilog 2005 () function.
git-svn-id: file://localhost/svn/verilator/trunk/verilator@1032 77ca24e4-aefa-0310-84f0-b9a241c72d87
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Wilson Snyder
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Changes
@ -5,6 +5,8 @@ indicates the contributor was also the author of the fix; Thanks!
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* Verilator 3.66***
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*** Add Verilog 2005 $clog2() function.
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**** Add error message when modules have duplicate names. [Stefan Thiede]
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**** Allow defines terminated in EOF, though against spec. [Stefan Thiede]
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@ -1003,6 +1003,8 @@ declarations inside port lists.
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Verilator supports the `begin_keywords and `end_keywords compiler
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directives.
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Verilator supports $clog2.
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Verilator partially supports the uwire keyword.
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=head1 SYSTEMVERILOG (IEEE 1800-2005) SUPPORT
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@ -495,6 +495,38 @@ static inline IData VL_REDXOR_64(QData r) {
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return r;
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}
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static inline IData VL_CLOG2_I(IData lhs) {
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// Perhaps can do better using fls GCC4 builtins
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int n=1;
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IData chk;
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if (!lhs) return 0;
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chk = lhs >> VL_UL(16); if (chk) { n += 16; lhs = chk; }
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chk = lhs >> VL_UL(8); if (chk) { n += 8; lhs = chk; }
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chk = lhs >> VL_UL(4); if (chk) { n += 4; lhs = chk; }
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chk = lhs >> VL_UL(2); if (chk) { n += 2; lhs = chk; }
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chk = lhs >> VL_UL(1); if (chk) { n += 1; lhs = chk; }
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return n;
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}
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static inline IData VL_CLOG2_Q(QData lhs) {
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// Perhaps can do better using fls GCC4 builtins
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int n=1;
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QData chk;
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if (!lhs) return 0;
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chk = lhs >> VL_ULL(32); if (chk) { n += 32; lhs = chk; }
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chk = lhs >> VL_ULL(16); if (chk) { n += 16; lhs = chk; }
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chk = lhs >> VL_ULL(8); if (chk) { n += 8; lhs = chk; }
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chk = lhs >> VL_ULL(4); if (chk) { n += 4; lhs = chk; }
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chk = lhs >> VL_ULL(2); if (chk) { n += 2; lhs = chk; }
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chk = lhs >> VL_ULL(1); if (chk) { n += 1; lhs = chk; }
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return n;
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}
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static inline IData VL_CLOG2_W(int words, WDataInP lwp) {
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for (int i=words-1; i>=0; i--) {
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if (lwp[i]) return VL_CLOG2_I(lwp[i])+i*VL_WORDSIZE;
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}
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return 0;
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}
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// EMIT_RULE: VL_COUNTONES_II: oclean = false; lhs clean
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static inline IData VL_COUNTONES_I(IData lhs) {
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IData r = lhs - ((lhs >> 1) & 033333333333) - ((lhs >> 2) & 011111111111);
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@ -1971,6 +1971,20 @@ struct AstUnsigned : public AstNodeUniop {
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virtual bool sizeMattersLhs() {return true;} // Eliminated before matters
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virtual int instrCount() const { return 0; }
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};
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struct AstCLog2 : public AstNodeUniop {
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AstCLog2(FileLine* fl, AstNode* lhsp) : AstNodeUniop(fl, lhsp) {}
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virtual ~AstCLog2() {}
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virtual AstType type() const { return AstType::CLOG2;}
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virtual AstNode* clone() { return new AstCLog2(*this); }
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virtual void accept(AstNVisitor& v, AstNUser* vup=NULL) { v.visit(this,vup); }
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virtual void numberOperate(V3Number& out, const V3Number& lhs) { out.opCLog2(lhs); }
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virtual string emitVerilog() { return "%k$clog2(%l)"; }
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virtual bool emitWordForm() { return true; }
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virtual string emitOperator() { return "VL_CLOG2"; }
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virtual bool cleanOut() {return false;} virtual bool cleanLhs() {return true;}
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virtual bool sizeMattersLhs() {return false;}
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virtual int instrCount() const { return widthInstrs()*16; }
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};
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struct AstCountOnes : public AstNodeUniop {
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// Number of bits set in vector
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AstCountOnes(FileLine* fl, AstNode* lhsp) : AstNodeUniop(fl, lhsp) {}
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@ -259,6 +259,7 @@ V3Number::V3Number (FileLine* fileline, const char* sourcep) {
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// Global
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int V3Number::log2b(uint32_t num) {
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// See also opCLog2
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for (int bit=31; bit>0; bit--) if (num & (VL_ULL(1)<<bit)) return(bit);
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return(0);
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}
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@ -621,6 +622,18 @@ V3Number& V3Number::opOneHot0 (const V3Number& lhs) {
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if (lhs.isFourState()) return setAllBitsX();
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return setSingleBits(lhs.countOnes()<=1);
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}
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V3Number& V3Number::opCLog2 (const V3Number& lhs) {
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if (lhs.isFourState()) return setAllBitsX();
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int bit;
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for (bit=lhs.width()-1; bit>=0; bit--) {
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if (lhs.bitIs1(bit)) {
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setLong(bit+1);
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return *this;
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}
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}
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setZero();
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return *this;
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}
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V3Number& V3Number::opLogNot (const V3Number& lhs) {
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// op i, 1 bit return
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@ -165,6 +165,7 @@ public:
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V3Number& opIsUnknown(const V3Number& lhs);
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V3Number& opOneHot (const V3Number& lhs);
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V3Number& opOneHot0 (const V3Number& lhs);
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V3Number& opCLog2 (const V3Number& lhs);
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V3Number& opClean (const V3Number& lhs, uint32_t bits);
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V3Number& opConcat (const V3Number& lhs, const V3Number& rhs);
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V3Number& opRepl (const V3Number& lhs, const V3Number& rhs);
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@ -70,6 +70,7 @@ private:
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virtual void visit(AstSel* nodep, AstNUser*) { signed_Ou_Ix(nodep); } //See backRequiresUnsigned
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virtual void visit(AstAttrOf* nodep, AstNUser*) { signed_Ou_Ix(nodep); }
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virtual void visit(AstCountOnes* nodep, AstNUser*) { signed_Ou_Ix(nodep); }
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virtual void visit(AstCLog2* nodep, AstNUser*) { signed_Ou_Ix(nodep); }
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virtual void visit(AstPslBool* nodep, AstNUser*) { signed_Ou_Ix(nodep); }
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virtual void visit(AstTime* nodep, AstNUser*) { signed_Ou_Ix(nodep); }
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//
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@ -378,6 +378,12 @@ private:
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// Just let all arguments seek their natural sizes
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nodep->iterateChildren(*this,WidthVP(ANYSIZE,0,BOTH).p());
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}
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virtual void visit(AstCLog2* nodep, AstNUser* vup) {
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if (vup->c()->prelim()) {
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nodep->lhsp()->iterateAndNext(*this,WidthVP(ANYSIZE,0,BOTH).p());
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nodep->width(32,32);
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}
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}
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virtual void visit(AstCountOnes* nodep, AstNUser* vup) {
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if (vup->c()->prelim()) {
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nodep->lhsp()->iterateAndNext(*this,WidthVP(ANYSIZE,0,BOTH).p());
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@ -313,6 +313,7 @@ escid \\[^ \t\f\r\n]+
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<S05,PSL>{
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/* System Tasks */
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"$bits" {yylval.fileline = CRELINE(); return yD_BITS;}
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"$clog2" {yylval.fileline = CRELINE(); return yD_CLOG2;}
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"$countones" {yylval.fileline = CRELINE(); return yD_COUNTONES;}
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"$error" {yylval.fileline = CRELINE(); return yD_ERROR;}
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"$fatal" {yylval.fileline = CRELINE(); return yD_FATAL;}
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@ -431,7 +432,7 @@ escid \\[^ \t\f\r\n]+
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/* Default PLI rule */
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<V95,V01,V05,S05,PSL>{
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"$"[a-zA-Z_$]+ {yyerrorf("Unsupported or unknown PLI call: %s",yytext);}
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"$"[a-zA-Z_$][a-zA-Z0-9_$]* {yyerrorf("Unsupported or unknown PLI call: %s",yytext);}
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}
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/************************************************************************/
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@ -220,6 +220,7 @@ class AstSenTree;
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%token<fileline> yD_BITS "$bits"
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%token<fileline> yD_C "$c"
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%token<fileline> yD_CLOG2 "$clog2"
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%token<fileline> yD_COUNTONES "$countones"
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%token<fileline> yD_DISPLAY "$display"
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%token<fileline> yD_ERROR "$error"
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@ -1072,6 +1073,7 @@ exprNoStr: expr yP_OROR expr { $$ = new AstLogOr ($2,$1,$3); }
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| yD_BITS '(' expr ')' { $$ = new AstAttrOf($1,AstAttrType::BITS,$3); }
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| yD_C '(' cStrList ')' { $$ = (v3Global.opt.ignc() ? NULL : new AstUCFunc($1,$3)); }
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| yD_CLOG2 '(' expr ')' { $$ = new AstCLog2($1,$3); }
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| yD_COUNTONES '(' expr ')' { $$ = new AstCountOnes($1,$3); }
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| yD_ISUNKNOWN '(' expr ')' { $$ = new AstIsUnknown($1,$3); }
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| yD_ONEHOT '(' expr ')' { $$ = new AstOneHot($1,$3); }
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@ -68,12 +68,12 @@ module t (/*AUTOARG*/
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endmodule
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module Test
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#(parameter SAMPLE_WIDTH = 4 )
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#(parameter SAMPLE_WIDTH = 5 )
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(
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`ifdef verilator // UNSUPPORTED
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output reg [2:0] pos,
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output reg [$clog2(SAMPLE_WIDTH-1)-1:0] pos,
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`else
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output reg [log2(SAMPLE_WIDTH)-1:0] pos,
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output reg [log2(SAMPLE_WIDTH-1)-1:0] pos,
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`endif
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// System
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input clk,
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18
test_regress/t/t_math_clog2.pl
Executable file
18
test_regress/t/t_math_clog2.pl
Executable file
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#!/usr/bin/perl
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if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
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# $Id$
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2003 by Wilson Snyder. This program is free software; you can
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# redistribute it and/or modify it under the terms of either the GNU
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# General Public License or the Perl Artistic License.
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compile (
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);
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execute (
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check_finished=>1,
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);
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ok(1);
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1;
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88
test_regress/t/t_math_clog2.v
Normal file
88
test_regress/t/t_math_clog2.v
Normal file
@ -0,0 +1,88 @@
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// $Id$
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2008 by Wilson Snyder.
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`ifdef verilator
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`define CLOG2 $clog2
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`else
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`define CLOG2 clog2_emulate
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`endif
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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integer cyc=0;
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reg [63:0] crc;
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reg [63:0] sum;
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wire [31:0] out = `CLOG2(crc[31:0]);
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wire [31:0] out2 = `CLOG2(crc);
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// Aggregate outputs into a single result vector
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wire [63:0] result = {out2, out};
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`define EXPECTED_SUM 64'hc402f59e3d971718
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// Test loop
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always @ (posedge clk) begin
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`ifdef TEST_VERBOSE
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$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
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`endif
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cyc <= cyc + 1;
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crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
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sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
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if (cyc==0) begin
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crc <= 64'h0;
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if (`CLOG2(32'h0) != 0) $stop;
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if (`CLOG2(32'h1) != 1) $stop;
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if (`CLOG2(32'h7) != 3) $stop;
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if (`CLOG2(32'h8) != 4) $stop;
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if (`CLOG2(32'h9) != 4) $stop;
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if (`CLOG2({32{1'b1}}) != 32) $stop;
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if (`CLOG2({64{1'b1}}) != 64) $stop;
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if (`CLOG2({128{1'b1}}) != 128) $stop;
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end
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else if (cyc==1) begin
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crc <= 64'h1;
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if (result != {32'd0, 32'd0}) $stop;
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end
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else if (cyc==2) begin
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crc <= 64'h3;
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if (result != {32'd1, 32'd1}) $stop;
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end
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else if (cyc==3) begin
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crc <= {64{1'b1}};
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if (result != {32'd2, 32'd2}) $stop;
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end
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else if (cyc==4) begin
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if (result != {32'd64, 32'd32}) $stop;
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end
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else if (cyc==8) begin
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crc <= 64'h5aef0c8d_d70a4497;
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end
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else if (cyc<10) begin
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sum <= 64'h0;
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end
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else if (cyc<90) begin
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end
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else if (cyc==99) begin
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$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
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if (crc !== 64'hcbc77bb9b3784ea0) $stop;
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if (sum !== `EXPECTED_SUM) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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function integer clog2_emulate(input [130:0] arg);
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begin
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for(clog2_emulate=0; arg>0; clog2_emulate=clog2_emulate+1)
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arg = (arg >> 1);
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end
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endfunction
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endmodule
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