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Internals: Refactor V3Inst static class. No functional change.
This commit is contained in:
Wilson Snyder
parent
a59639413d
commit
9542783a7e
164
src/V3Inst.cpp
164
src/V3Inst.cpp
@ -239,81 +239,103 @@ public:
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virtual ~InstDeVisitor() {}
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};
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//######################################################################
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// Inst static function
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class InstStatic {
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private:
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static int debug() {
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static int level = -1;
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if (VL_UNLIKELY(level < 0)) level = v3Global.opt.debugSrcLevel(__FILE__);
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return level;
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}
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InstStatic() {} // Static class
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static AstNode* extendOrSel(FileLine* fl, AstNode* rhsp, AstNode* cmpWidthp) {
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if (cmpWidthp->width() > rhsp->width()) {
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rhsp = (rhsp->isSigned()
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? (new AstExtendS(fl, rhsp))->castNode()
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: (new AstExtend (fl, rhsp))->castNode());
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} else if (cmpWidthp->width() < rhsp->width()) {
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rhsp = new AstSel (fl, rhsp, 0, cmpWidthp->width());
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}
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rhsp->dtypeFrom(cmpWidthp); // Need proper widthMin, which may differ from AstSel created above
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return rhsp;
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}
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public:
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static AstAssignW* pinReconnectSimple(AstPin* pinp, AstCell* cellp, AstNodeModule*,
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bool forTristate, bool alwaysCvt) {
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// If a pin connection is "simple" leave it as-is
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// Else create a intermediate wire to perform the interconnect
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// Return the new assignment, if one was made
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// Note this module calles cloneTree() via new AstVar
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AstVar* pinVarp = pinp->modVarp();
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AstVarRef* connectRefp = pinp->exprp()->castVarRef();
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AstBasicDType* pinBasicp = pinVarp->dtypep()->basicp(); // Maybe NULL
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AstBasicDType* connBasicp = NULL;
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AstAssignW* assignp = NULL;
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if (connectRefp) connBasicp = connectRefp->varp()->dtypep()->basicp();
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//
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if (!alwaysCvt
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&& connectRefp
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&& connectRefp->varp()->dtypep()->sameTree(pinVarp->dtypep())
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&& !connectRefp->varp()->isSc()) { // Need the signal as a 'shell' to convert types
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// Done. Same data type
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} else if (!alwaysCvt
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&& connectRefp
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&& connectRefp->varp()->isIfaceRef()) {
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// Done. Interface
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} else if (!alwaysCvt
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&& connBasicp
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&& pinBasicp
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&& connBasicp->width() == pinBasicp->width()
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&& connBasicp->lsb() == pinBasicp->lsb()
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&& !connectRefp->varp()->isSc() // Need the signal as a 'shell' to convert types
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&& connBasicp->width() == pinVarp->width()
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&& 1) {
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// Done. One to one interconnect won't need a temporary variable.
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} else if (!alwaysCvt && !forTristate && pinp->exprp()->castConst()) {
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// Done. Constant.
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} else {
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// Make a new temp wire
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//if (1||debug()>=9) { pinp->dumpTree(cout,"-in_pin:"); }
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AstNode* pinexprp = pinp->exprp()->unlinkFrBack();
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string newvarname = ((string)(pinVarp->isOutput() ? "__Vcellout" : "__Vcellinp")
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+(forTristate?"t":"") // Prevent name conflict if both tri & non-tri add signals
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+"__"+cellp->name()+"__"+pinp->name());
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AstVar* newvarp = new AstVar (pinVarp->fileline(), AstVarType::MODULETEMP, newvarname, pinVarp);
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// Important to add statement next to cell, in case there is a generate with same named cell
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cellp->addNextHere(newvarp);
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if (pinVarp->isInout()) {
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pinVarp->v3fatalSrc("Unsupported: Inout connections to pins must be direct one-to-one connection (without any expression)");
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} else if (pinVarp->isOutput()) {
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// See also V3Inst
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AstNode* rhsp = new AstVarRef(pinp->fileline(), newvarp, false);
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rhsp = extendOrSel (pinp->fileline(), rhsp, pinVarp);
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assignp = new AstAssignW (pinp->fileline(), pinexprp, rhsp);
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pinp->exprp(new AstVarRef (pinexprp->fileline(), newvarp, true));
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} else {
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// V3 width should have range/extended to make the widths correct
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assignp = new AstAssignW (pinp->fileline(),
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new AstVarRef(pinp->fileline(), newvarp, true),
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pinexprp);
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pinp->exprp(new AstVarRef (pinexprp->fileline(), newvarp, false));
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}
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if (assignp) cellp->addNextHere(assignp);
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//if (debug()) { pinp->dumpTree(cout,"- out:"); }
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//if (debug()) { assignp->dumpTree(cout,"- aout:"); }
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}
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return assignp;
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}
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};
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//######################################################################
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// Inst class functions
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AstAssignW* V3Inst::pinReconnectSimple(AstPin* pinp, AstCell* cellp, AstNodeModule*,
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AstAssignW* V3Inst::pinReconnectSimple(AstPin* pinp, AstCell* cellp, AstNodeModule* modp,
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bool forTristate, bool alwaysCvt) {
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// If a pin connection is "simple" leave it as-is
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// Else create a intermediate wire to perform the interconnect
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// Return the new assignment, if one was made
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// Note this module calles cloneTree() via new AstVar
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AstVar* pinVarp = pinp->modVarp();
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AstVarRef* connectRefp = pinp->exprp()->castVarRef();
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AstBasicDType* pinBasicp = pinVarp->dtypep()->basicp(); // Maybe NULL
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AstBasicDType* connBasicp = NULL;
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AstAssignW* assignp = NULL;
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if (connectRefp) connBasicp = connectRefp->varp()->dtypep()->basicp();
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//
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if (!alwaysCvt
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&& connectRefp
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&& connectRefp->varp()->dtypep()->sameTree(pinVarp->dtypep())
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&& !connectRefp->varp()->isSc()) { // Need the signal as a 'shell' to convert types
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// Done. Same data type
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} else if (!alwaysCvt
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&& connectRefp
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&& connectRefp->varp()->isIfaceRef()) {
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// Done. Interface
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} else if (!alwaysCvt
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&& connBasicp
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&& pinBasicp
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&& connBasicp->width() == pinBasicp->width()
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&& connBasicp->lsb() == pinBasicp->lsb()
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&& !connectRefp->varp()->isSc() // Need the signal as a 'shell' to convert types
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&& connBasicp->width() == pinVarp->width()
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&& 1) {
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// Done. One to one interconnect won't need a temporary variable.
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} else if (!alwaysCvt && !forTristate && pinp->exprp()->castConst()) {
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// Done. Constant.
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} else {
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// Make a new temp wire
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//if (1||debug()>=9) { pinp->dumpTree(cout,"-in_pin:"); }
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AstNode* pinexprp = pinp->exprp()->unlinkFrBack();
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string newvarname = ((string)(pinVarp->isOutput() ? "__Vcellout" : "__Vcellinp")
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+(forTristate?"t":"") // Prevent name conflict if both tri & non-tri add signals
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+"__"+cellp->name()+"__"+pinp->name());
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AstVar* newvarp = new AstVar (pinVarp->fileline(), AstVarType::MODULETEMP, newvarname, pinVarp);
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// Important to add statement next to cell, in case there is a generate with same named cell
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cellp->addNextHere(newvarp);
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if (pinVarp->isInout()) {
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pinVarp->v3fatalSrc("Unsupported: Inout connections to pins must be direct one-to-one connection (without any expression)");
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} else if (pinVarp->isOutput()) {
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// See also V3Inst
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AstNode* rhsp = new AstVarRef(pinp->fileline(), newvarp, false);
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if (pinVarp->width() > rhsp->width()) {
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if (rhsp->isSigned()) {
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rhsp = new AstExtendS(pinp->fileline(), rhsp);
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} else {
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rhsp = new AstExtend (pinp->fileline(), rhsp);
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}
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} else if (pinVarp->width() < rhsp->width()) {
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rhsp = new AstSel (pinp->fileline(), rhsp, 0, pinVarp->width());
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}
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rhsp->dtypeFrom(pinVarp); // Need proper widthMin, which may differ from AstSel created above
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assignp = new AstAssignW (pinp->fileline(), pinexprp, rhsp);
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pinp->exprp(new AstVarRef (pinexprp->fileline(), newvarp, true));
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} else {
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// V3 width should have range/extended to make the widths correct
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assignp = new AstAssignW (pinp->fileline(),
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new AstVarRef(pinp->fileline(), newvarp, true),
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pinexprp);
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pinp->exprp(new AstVarRef (pinexprp->fileline(), newvarp, false));
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}
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if (assignp) cellp->addNextHere(assignp);
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//if (debug()) { pinp->dumpTree(cout,"- out:"); }
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//if (debug()) { assignp->dumpTree(cout,"- aout:"); }
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}
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return assignp;
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return InstStatic::pinReconnectSimple(pinp, cellp, modp, forTristate, alwaysCvt);
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}
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//######################################################################
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@ -3005,9 +3005,10 @@ private:
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// which bits to truncate.
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AstNodeAssign* assignp = nodep->castNodeAssign();
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AstPin* pinp = nodep->castPin();
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if (assignp && assignp->lhsp()->castNodeStream()) { }
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else if (pinp && !pinp->modVarp()->isInput()) { }
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else {
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if (assignp && assignp->lhsp()->castNodeStream()) {
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} else if (pinp && !pinp->modVarp()->isInput()) { // V3Inst::pinReconnectSimple must deal
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UINFO(5,"pinInSizeMismatch: "<<pinp);
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} else {
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fixWidthExtend(underp, expDTypep, extendRule); underp=NULL;//Changed
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}
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}
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