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Internals: Port parsing cleanups
This commit is contained in:
Wilson Snyder
parent
abd4c480cd
commit
94fd17e4f7
@ -292,7 +292,7 @@ class LinkParseVisitor final : public VNVisitor {
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nodep->v3warn(STATICVAR, "Static variable with assignment declaration declared in a "
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"loop converted to automatic");
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}
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if (nodep->varType() != VVarType::PORT) {
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if (!nodep->direction().isAny()) { // Not a port
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if (nodep->lifetime().isNone()) {
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if (m_lifetimeAllowed) {
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nodep->lifetime(m_lifetime);
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@ -487,8 +487,9 @@ class TristateVisitor final : public TristateBaseVisitor {
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// Return the master __en for the specified input variable
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if (!invarp->user1p()) {
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AstVar* const newp
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= new AstVar{invarp->fileline(), isTop ? VVarType::PORT : VVarType::MODULETEMP,
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= new AstVar{invarp->fileline(), isTop ? VVarType::VAR : VVarType::MODULETEMP,
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invarp->name() + "__en", invarp};
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// Inherited VDirection::INPUT
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UINFO(9, " newenv " << newp << endl);
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modAddStmtp(invarp, newp);
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invarp->user1p(newp); // find envar given invarp
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@ -540,8 +541,9 @@ class TristateVisitor final : public TristateBaseVisitor {
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// Return the master __out for the specified input variable
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if (!m_varAux(invarp).outVarp) {
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AstVar* const newp
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= new AstVar{invarp->fileline(), isTop ? VVarType::PORT : VVarType::MODULETEMP,
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= new AstVar{invarp->fileline(), isTop ? VVarType::VAR : VVarType::MODULETEMP,
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invarp->name() + "__out", invarp};
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// Inherited VDirection::OUTPUT
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UINFO(9, " newout " << newp << endl);
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modAddStmtp(invarp, newp);
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m_varAux(invarp).outVarp = newp; // find outvar given invarp
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@ -89,8 +89,8 @@ public:
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FileLine* m_instModuleFl = nullptr; // Fileline of module referenced for instantiations
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AstPin* m_instParamp = nullptr; // Parameters for instantiations
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string m_instModule; // Name of module referenced for instantiations
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VVarType m_varDecl; // Type for next signal declaration (reg/wire/etc)
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VDirection m_varIO; // Direction for next signal declaration (reg/wire/etc)
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VVarType m_varDecl = VVarType::UNKNOWN; // Type for next signal declaration (reg/wire/etc)
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VDirection m_varIO = VDirection::NONE; // Direction for next signal declaration (reg/wire/etc)
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VLifetime m_varLifetime; // Static/Automatic for next signal
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bool m_impliedDecl = false; // Allow implied wire declarations
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bool m_varDeclTyped = false; // Var got reg/wire for dedup check
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@ -110,10 +110,7 @@ public:
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static int s_modTypeImpNum; // Implicit type number, incremented each module
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// CONSTRUCTORS
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V3ParseGrammar() {
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m_varDecl = VVarType::UNKNOWN;
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m_varIO = VDirection::NONE;
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}
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V3ParseGrammar() {}
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static V3ParseGrammar* singletonp() {
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static V3ParseGrammar singleton;
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return &singleton;
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@ -203,7 +200,6 @@ public:
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<< name << "'");
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}
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}
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void setVarDecl(VVarType type) { m_varDecl = type; }
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void setDType(AstNodeDType* dtypep) {
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if (m_varDTypep) VL_DO_CLEAR(m_varDTypep->deleteTree(), m_varDTypep = nullptr);
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m_varDTypep = dtypep;
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@ -312,28 +308,19 @@ int V3ParseGrammar::s_modTypeImpNum = 0;
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#define CRELINE() (PARSEP->bisonLastFileline()->copyOrSameFileLineApplied())
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#define FILELINE_OR_CRE(nodep) ((nodep) ? (nodep)->fileline() : CRELINE())
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#define VARRESET_LIST(decl) \
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#define VARRESET_LIST(decl) VARRESET__PVT(decl, 1) // Start of pinlist
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#define VARRESET_NONLIST(decl) VARRESET__PVT(decl, 0); // Not in a pinlist
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#define VARRESET__PVT(decl, pinNumStart) \
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{ \
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GRAMMARP->m_pinNum = 1; \
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VARRESET(); \
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VARDECL(decl); \
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} // Start of pinlist
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#define VARRESET_NONLIST(decl) \
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{ \
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GRAMMARP->m_pinNum = 0; \
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VARRESET(); \
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VARDECL(decl); \
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} // Not in a pinlist
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#define VARRESET() \
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{ \
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VARDECL(UNKNOWN); \
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VARIO(NONE); \
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VARDTYPE_NDECL(nullptr); \
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GRAMMARP->m_pinNum = (pinNumStart); \
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GRAMMARP->m_varLifetime = VLifetime::NONE; \
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GRAMMARP->m_varDeclTyped = false; \
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}
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#define VARDECL(type) \
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{ GRAMMARP->setVarDecl(VVarType::type); }
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{ GRAMMARP->m_varDecl = VVarType::type; }
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#define VARIO(type) \
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{ GRAMMARP->m_varIO = VDirection::type; }
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#define VARLIFE(flag) \
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@ -1478,10 +1465,10 @@ portsStarE<nodep>: // IEEE: .* + list_of_ports + list_of_port_decla
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| '(' ')' { $$ = nullptr; }
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// // .* expanded from module_declaration
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//UNSUP '(' yP_DOTSTAR ')' { UNSUP }
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| '(' { VARRESET_LIST(PORT);
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GRAMMARP->m_pinAnsi = true; }
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/*cont*/ list_of_ports ')' { $$ = $3; VARRESET_NONLIST(UNKNOWN);
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GRAMMARP->m_pinAnsi = false; }
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| '('
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/*mid*/ { VARRESET_LIST(PORT); GRAMMARP->m_pinAnsi = true; }
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/*cont*/ list_of_ports ')'
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{ $$ = $3; VARRESET_NONLIST(UNKNOWN); GRAMMARP->m_pinAnsi = false; }
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;
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list_of_portsE<nodep>: // IEEE: list_of_ports + list_of_port_declarations
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@ -1499,7 +1486,7 @@ portAndTagE<nodep>:
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{ int p = PINNUMINC();
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const string name = "__pinNumber" + cvtToStr(p);
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$$ = new AstPort{CRELINE(), p, name};
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AstVar* varp = new AstVar{CRELINE(), VVarType::PORT, name, VFlagChildDType{},
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AstVar* varp = new AstVar{CRELINE(), VVarType::WIRE, name, VFlagChildDType{},
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new AstBasicDType{CRELINE(), LOGIC_IMPLICIT}};
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varp->declDirection(VDirection::INPUT);
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varp->direction(VDirection::INPUT);
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@ -3796,7 +3783,7 @@ statementFor<beginp>: // IEEE: part of statement
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$$->addStmtsp(new AstWhile{$1, new AstConst{$1, AstConst::BitTrue{}}, $7, $5}); }
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;
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beginForParen: // IEEE: Part of statement (for loop beginning paren)
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'(' { VARRESET(); }
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'(' { VARRESET_NONLIST(UNKNOWN); }
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;
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statementVerilatorPragmas<nodep>:
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@ -5449,7 +5436,7 @@ let_declaration<letp>: // IEEE: let_declaration
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let_port_listE<nodep>: // IEEE: [ let_port_list ]
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/*empty*/ { $$ = nullptr; }
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| /*emptyStart*/
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/*mid*/ { VARRESET_LIST(UNKNOWN); VARIO(INOUT); }
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/*mid*/ { VARRESET_LIST(VAR); VARIO(INOUT); }
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/*cont*/ let_port_list { $$ = $2; VARRESET_NONLIST(UNKNOWN); }
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;
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@ -5461,7 +5448,7 @@ let_port_list<nodep>: // IEEE: let_port_list
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let_port_item<varp>: // IEEE: let_port_Item
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// // IEEE: Expanded let_formal_type
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yUNTYPED idAny/*formal_port_identifier*/ variable_dimensionListE exprEqE
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{ $$ = new AstVar{$<fl>2, VVarType::PORT, *$2, VFlagChildDType{},
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{ $$ = new AstVar{$<fl>2, VVarType::VAR, *$2, VFlagChildDType{},
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new AstBasicDType{$<fl>2, LOGIC_IMPLICIT}};
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$$->direction(VDirection::INOUT);
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$$->lifetime(VLifetime::AUTOMATIC);
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@ -5469,7 +5456,7 @@ let_port_item<varp>: // IEEE: let_port_Item
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PINNUMINC(); }
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| data_type idAny/*formal_port_identifier*/ variable_dimensionListE exprEqE
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{ BBUNSUP($<fl>1, "Unsupported: let typed ports");
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$$ = new AstVar{$<fl>2, VVarType::PORT, *$2, VFlagChildDType{},
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$$ = new AstVar{$<fl>2, VVarType::VAR, *$2, VFlagChildDType{},
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new AstBasicDType{$<fl>2, LOGIC_IMPLICIT}};
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$$->direction(VDirection::INOUT);
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$$->lifetime(VLifetime::AUTOMATIC);
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@ -5477,7 +5464,7 @@ let_port_item<varp>: // IEEE: let_port_Item
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PINNUMINC(); }
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| implicit_typeE id/*formal_port_identifier*/ variable_dimensionListE exprEqE
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{ if ($1) BBUNSUP($<fl>1, "Unsupported: let typed ports");
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$$ = new AstVar{$<fl>2, VVarType::PORT, *$2, VFlagChildDType{},
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$$ = new AstVar{$<fl>2, VVarType::VAR, *$2, VFlagChildDType{},
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new AstBasicDType{$<fl>2, LOGIC_IMPLICIT}};
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$$->direction(VDirection::INOUT);
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$$->lifetime(VLifetime::AUTOMATIC);
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